Where is the new low end in FPGAs?
In basic terms, standard digital logic takes the form of dedicated gates in a single package. Programmable read-only memories (PROMs) can be used as look-up tables, a simple solution to more configurable logical functionality. Programmable logic devices take this to the next level, using arrays of logic gates with programmable interconnects.
Even a simple programmable logic device (PLD) can implement complex sum-of-products Boolean expressions. These devices offer functional integration at the cost of configuration. Configuring these devices also evolved. Permanently blowing a fuse has given way to storing values in reprogrammable memory.
PLDs succeed, in part, because they provide greater functional integration in a familiar design paradigm. Engineering methodologies have moved seamlessly forward while still supporting conventional techniques such as schematic capture. But the relentless march of Moore’s Law means designers want even higher functional integration.
The complex PLD (CPLD) achieves this with another paradigm shift, integrating multiple PLDs and more routing resources into a single device. Designers can extend their familiar design paradigm to another generation of devices. This complexity comes at the cost of hierarchical routing schemes and timing issues, inherent with larger designs.
The FPGA product offering continues to evolve
Programmable logic offers high levels of flexibility and performance. Engineers can take advantage of the providers’ roadmap to access more capabilities without changing their entire development process.
Tackling complexity with FPGAs
As designs grow, it becomes difficult to leverage CPLDs using traditional design entry tools such as schematic capture. One alternative is the full-custom application-specific IC (ASIC). An ASIC vendor customizes every layer of a chip, which makes the integrated circuit relatively low cost in high volumes, but the design process is comparatively expensive. It also comes with additional financial risk of committing to large orders and longer design times.
The gate array is an intermediate step between standard parts and full custom ASICs. The IC vendor creates wafers that feature a sea of uncommitted logic gates. Customers design masks to define the metal interconnect layers, implementing their functionality. This approach still comes with trade-offs between functional density, time to market, risk, and design complexity.
The field-programmable gate array (FPGA) removes mask-based interconnects, replacing them with a programmable fabric. An FPGA combines the functional advantages of a gate array with the prototyping convenience and risk mitigation of a CPLD.
The FPGA features more complex logic and multiple configurable logic blocks. As with large CPLDs, FPGAs offer a hierarchy of programmable interconnects. This hierarchy enables complex functionality but at the cost of even more challenging timing issues.
The emergence of FPGAs coincided with the introduction of hardware description languages (HDLs). Rather than schematic diagrams, an HDL uses text to describe a design. HDLs offer productivity improvements and enable the use of more rigorous simulation and verification processes to prove a design’s validity.
The adoption of HDLs was also a paradigm shift, breaking down the direct relationship between design intent and implementation. Rather than wiring between gates on a schematic, logic-synthesis tools are used to interpret an HDL description into gates. Other software tools then map the gate-level design to the resources of the FPGA, and route them through the interconnect.
FPGA architectures continue to become better targets for logic synthesis, placement, routing, and timing tools. Vendors have developed more efficient logic blocks and advanced routing architectures to ease design flows. Better architectures allow greater predictability about key figures of merit, such as resource utilization and overall performance.
Moore's law has enabled FPGAs to expand to millions of logic gates, include richer routing resources, and larger amounts of local memory. It is now practical to integrate specialized functional blocks and multiple processor cores alongside programmable gates, to realize complex systems on a chip (SoCs) on an FPGA.
The latest FPGAs combine performance and efficiency
Take a closer look at the latest FPGAs. The combination of performance and efficiency may surprise you.
FPGAs keep getting bigger and better
All large designs face the same problem. The productivity gap gets wider. The response from FPGA vendors started with soft intellectual property (IP) blocks. These software blocks, often provided free of charge, include popular functions that can be instantiated in the FPGA’s resources to deliver proven functionality and performance. Most FPGA providers now also provide soft IP blocks to instantiate entire processor sub-systems in this way.
While popular, integrating processors using soft IP is relatively inefficient. FPGA vendors moved to solutions that included key functional blocks, such as general-purpose processors, DSPs, and extra memory, as hard IP. These transistor-level functions are physically placed within the wider FPGA fabric.
Using hard-wired functions that cannot be realized purely in logic gates helps bridge the design gap, offering more efficient implementations than soft IP alternatives. These SoC FPGAs are functional powerhouses, optimized for certain applications such as algorithmic acceleration or communications processing.
FPGAs are also an important way for chip foundries to prove their processes. The performance requirements and die sizes required test the leading edge of IC manufacture. Large SoC FPGA designs also test operational issues such as powering and cooling the devices effectively.
Most recently, leading FPGA providers have been working with foundries to pioneer new packaging techniques. Chiplets are small functional circuits built on standalone silicon. The chiplet is directly, or very nearly directly, integrated with the FPGA die.
One of the most striking examples of chiplets used in FPGAs to date has been the integration of four separate very high-speed optical transceivers on an SoC FPGA die to create a highly effective communications processor in one package.
Where is the new low end in FPGAs?
To return to the question, what does it mean when leading programmable-logic vendors discontinue some low-end parts, and how should designers feel about it? The reality is, the low-end hasn’t disappeared, it has simply moved.
As this article explains, programmable logic has evolved in response to the way electronic design has changed. Today’s SoC FPGAs are the result of a tremendously innovative market. FPGA vendors are providing designers with a wide variety of architectures, to realize arbitrary digital logic in the fixed resources of a physical chip.
The product offerings from FPGA vendors are constantly optimized to best meet the market’s needs. Design engineers can set their sights higher, choosing partners who can help them select the best programmable device for their next design. Avnet works with multiple programmable logic vendors and has experienced engineers available to help customers get the most out of each of them.