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The advent of the inter-connected world brings innovations ranging from ubiquitous consumer broadband to ultra-low latency wireless vehicular communication and massive machine-type communications, all in constant pursuit of wider bandwidth and better signal fidelity. Meanwhile constraints on size, weight, power and programmability demand higher levels of integration within the system. Combining up to 16 channels of integrated multi-gigasample RF data converters with an Arm® Cortex®-A53 processing subsystem and AMD UltraScale+™ programmable logic, AMD Zynq™ RFSoC takes center stage in this webinar series.

Starting with an introduction to the AMD RFSoC architecture and progressing towards system design with RF front-ends, you will learn practical design techniques including frequency-planning, multi-channel data converter synchronization, and advanced test and measurement solutions for 5G FR2 mmWave bands.

AMD Zynq - GBL
AMD Zynq™ RFSoC DFE

AMD Zynq™ RFSoC DFE technology in O-RU radio solutions

Discover the transformative power of AMD Zynq™ RFSoC DFE technology in O-RU radio. This webinar covers the AMD Zynq™ RFSoC DFE devices down to the basic architecture and provides an overview of the AMD ecosystem.

5G FR2 - GBL
5G connectivity illustration

Prototype 5G FR2 with the AMD Zynq™ RFSoC DFE and mmWave Phased Array

Engineers from Avnet, AMD and Rohde & Schwarz describe a new 5G FR2 phased array antenna-to-bits development system and demonstrate automated OTA measurements using a CATR benchtop antenna test system.

EVM - GBL
satellite tower

Optimizing EVM Measurements in 5G FR2 Phased Array Antenna Modules

Learn RF measurement techniques for optimal OTA wireless link performance using the R&S® ATS800B CATR benchtop antenna test system. The device-under-test combines the AMD Zynq™ RFSoC DFE, MATLAB-based 5G NR signal generation.

Multi-tile Sync - GBL
streaks of light

Multi-Tile Sync Characterization on AMD Zynq™ UltraScale+™ RFSoC Gen 3

This webinar reviews the AMD Zynq™ RFSoC data converter structure & recent multi-tile synch characterization, plus a design methodology using HDL CoderTM from MathWorks for custom implementations on the AMD Zynq UltraScale+™ ZCU208 Evaluation Kit