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Programmable logic Reference Designs

Programmable logic components are used to build reconfigurable digital circuits, shortening development cycles for manufacturers, and helping them get their product to the market faster. Explore our articles and information on the latest in CPLDs, FP
Reference Design Block Diagram of 65W Multi-Port (USB Type-C and USB Type-A) Power Delivery based on STMicroelectronics Solution
The EVLONEMP is one of the best power density USB Power Delivery multiport boards with a USB Type-A port and a USB Type-C port supporting Programmable Power Supply (PPS).
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Reference Design Block Diagram of 65W USB Type-C Power Delivery Reference Design based on STMicroelectronics Solution
The EVLVIPGAN65PD is a 65 W USB Type-C Power Delivery 3.0 adapter reference design. It is an isolated power supply with a standalone USB PD controller.
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Reference Design Block Diagram of 65W USB-PD Evaluation Board based on onsemi Solution
The NCP1345PD65WGEVB is the 65 W, USB PD type-C PD3.0/ PPS charger solution.
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Reference Design Block Diagram of AI Camera and Voice Recognition Solution based on Renesas Solution
Reference Design of a smart motor driving circuit, using the RA6T2 MCU and RAA227063 3-phase smart driver for processing speed and power efficiency to address traction of the motors
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Reference Design Block Diagram of AIoT Application Development Kit based on ISSI's T31-INDUS Solution
This development kit consists of development boards (core module, WIFI module, and sensor board), an operating system, and an SDK package.
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Reference Design Block Diagram of AMD Artix 7 Power Tree based on onsemi Solution
The AMD Artix 7 Power Tree is a power management solution that provides the necessary power rails to the FPGA using onsemi's key power devices.
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Reference Design Block Diagram of AMD Artix 7 Starter Recipe
Starter Recipe for the AMD Artix-7 family of cost and transceiver optimized FPGAs.
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Reference Design Block Diagram of AMD Artix UltraScale+ (AU10P-AU15P) Power Tree based on onsemi Solution
The AMD Artix UltraScale+ (AU10P/AU15P) Power Tree is a power management solution for the Artix UltraScale+ FPGA Family using onsemi's key power devices.
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Reference Design Block Diagram of AMD Artix UltraScale+ PMIC Low-Power Design based on AnDAPT Solution
Low-power reference design for AMD's Artix UltraScale+ AU10P, AU15P, AU20P, and AU25P families.
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Reference Design Block Diagram of AMD Artix UltraScale+ Starter Recipe
Artix UltraScale+ devices are the industry only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance....
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Reference Design Block Diagram of AMD Artix US+ Low Power Tree based on AnDAPT Solution
The ARD_X_AUP_A1 is a scalable power supply designed to provide power to Xilinx Artix UltraScale+ Low power FPGA devices.
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Reference Design Block Diagram of AMD Artix-7 High Power Tree based on AnDAPT Solution
The ARD_X_AX7_B1 is a scalable power supply designed to provide power to Xilinx Artix-7 High-Power FPGA devices.
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Reference Design Block Diagram of AMD Artix-7 Medium Low Power Tree based on AnDAPT Solution
The ARD_X_AX7_A1 is a scalable power supply designed to provide power to Xilinx Artix-7 Medium/Low power FPGA devices. The design is scalable to support devices.
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Reference Design Block Diagram of AMD Kintex UltraScale (KU035-KU075) Power Tree based on onsemi Solution
The AMD Kintex UltraScale (KU035/KU076) Power Tree is a power management solution for the Kintex UltraScale FPGAs using onsemi's key power devices.
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Reference Design Block Diagram of AMD Kintex UltraScale (KU100) Power Tree based on onsemi Solution
The AMD Kintex UltraScale (KU100) Power Tree is a power management solution for the Kintex UltraScale FPGAs using onsemi's key power devices.
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Reference Design Block Diagram of AMD Kintex UltraScale+ Starter Recipe
Kintex UltraScale+ devices provide the best price/performance/watt balance in a FinFET node.
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Reference Design Block Diagram of AMD Kintex US+ Minimun Rails Power Tree based on AnDAPT Solution
The ARD_X_KUP_A is a scalable power supply designed to provide power to Xilinx Kintex UltraScale+ devices.
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Reference Design Block Diagram of AMD Kintex-7 Power Tree based on AnDAPT Solution
The ARD_X_KX7_C1 is a scalable power supply designed to provide power to Xilinx Kintex-7 FPGAs without MGT (Multi-Gigabit Transceiver) rails. The design is scalable and flexible to support the FPGA.
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Reference Design Block Diagram of AMD Kintex-7 with MGT Power Tree based on AnDAPT Solution
The ARD_X_KX7_C2 is a scalable power supply designed to provide power to Xilinx Kintex-7 FPGAs with MGT (Multi-Gigabit Transceiver) rails. The design is scalable and flexible to support the FPGA.
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Reference Design Block Diagram of AMD Spartan 7 Power Rails based on TDK uPOL Module Solution
AMD Spartan 7 FPGAS Power rails based on TDK uPOL Power Modules Solution, saving space and design time without compromising in performance.
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Reference Design Block Diagram of AMD Spartan 7 Power Tree based on onsemi Solution
The AMD Spartan 7 Power Tree is a power management solution that provides the necessary power rails to the FPGA using onsemi's key power devices.
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Reference Design Block Diagram of AMD Spartan 7 Starter Recipe
Spartan-7 devices offer the best in class performance per watt, along with small form factor packaging to meet the most stringent requirements
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Reference Design Block Diagram of AMD Versal AI Starter Recipe
Starter Recipe for the AMD Versal AI family of ACAP devices.
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Reference Design Block Diagram of AMD Versal Premium Lower Loading Power Tree based on AnDAPT Solution
The ARD_X_VRPM_A is a scalable power supply designed to provide power to AMD Versal Premium Lower Loading FPGA devices. The designs is scalable to support the cost- and power-optimized FPGA devices.
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Reference Design Block Diagram of AMD Versal Premium Starter Recipe
Starter Recipe for AMD Versal Premium family of ACAP devices.
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Reference Design Block Diagram of AMD Versal Premium Upper Loading Power Tree based on AnDAPT Solution
The ARD_X_VRPM_B is a scalable power supply designed to provide power to AMD Versal Premium Upper Loading FPGA devices. The designs is scalable to support the cost- and power-optimized FPGA devices.
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Reference Design Block Diagram of AMD Versal Prime Starter Recipe
Starter Recipe for AMD's Versal Prime family of ACAP devices.
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Reference Design Block Diagram of AMD Versal Prime VM1102-VM2602 Al Core VC1352 Power Use Case 2 based on Infineon Solution
Provides the perfect development environment for evaluating the unprecedented levels of performance, system integration and bandwidth provided by Virtex UltraScale devices.
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Reference Design Block Diagram of AMD Virtex UltraScale (VU080-VU095) Power Tree based on onsemi Solution
The AMD Virtex UltraScale (VU080/VU095) Power Tree is a power management solution for the Virtex UltraScale FPGAs using onsemi's key power devices.
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Reference Design Block Diagram of AMD Virtex UltraScale+ (VU11P-VU13P) Power Tree based on onsemi Solution
The AMD Virtex UltraScale+ (VU11P/VU13P) power solution is a general-purpose power tree for the Virtex UltraScale+ series of FPGAs using onsemi's key power devices.
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