New Product Introduction

NPI Body

NXP Semiconductors i.MX RT1170

i.MX RT1170 crossover MCU - ushering in the GHz MCU Era

The i.MX RT1170 MCU family features four target pillars that really set it apart, with its GHz performance, advanced security, rich feature set, and low-power. It is a dual-core device boasting a 1 GHz Arm® Cortex®-M7 and a 400 MHz Cortex®-M4. Both cores include a good amount of tightly coupled memory that further improves overall system performance. It has advanced security features along with up to 2MB SRAM, and 2D HW GPU, 2 Gigabit Ethernet ports (and one 10/100), 2 HS USB OTG with PHY, and support for a MIPI display and camera. The i.MX RT1170 is manufactured in 28-nm FD-SOI technology, optimized for both active power and leakage power.

Key features

Performance: 1 GHz Arm® Cortex®-M7 with 512 KB TCM / 400 MHz Cortex®-M4 with 256KB TCM
Security: Secure Boot, Crypto, Encryption Engine, On-The-Fly AES Decryption, Tamper Detect
Rich Integration: 2 MB SRAM, 2D GPU and 2D Accelerator, MIPI CSI/DSI, 2x 1 Gbps Ethernet
Low Power: 28nm FD-SOI Process, Optimized for both active power & leakage power

Additional features

Arm^®Cortex^®-M7 processor, 1 GHz, 32 KB/32 KB L1 Cache, 512 KB TCM
Arm^® Cortex^®-M4 processor, 400 MHz, 16 KB/16 KB L1 Cache, 256 KB TCM
2MB on-chip SRAM (including TCM for CPU core)
Parallel LCD Display up to WXGA (1280x800) at 60 FPS
8/16/24-bit Parallel Camera Sensor Interface
2-lane MIPI CSI and 2-lane MIPI DSI
2D GPU & Graphics Accelerator
8/16/32-bit SDRAM controller up to 200 MHz
8/16-bit Parallel NOR FLASH / NAND FLASH / SRAM
2x Dual-channel FlexSPI Interfaces with On-the-Fly decryption, supporting serial NOR, serial NAND, HyperBUS devices
2x eMMC 5.0/SD 3.0/SDIO Port
2x USB 2.0 OTG, HS/FS, Device or Host with PHY
Audio: 4x I2S/SAI, 1x S/PDIF Tx/Rx, ASRC, 8-ch digital microphone input
3x ENET: 1 Gbps ENET w/ AVB + 10/100 ENET w/ IEEE 1588 + 1 Gbps ENET w/ TSN
2x 12-bit ADC, 4.2 MSPS, up to 20 input channels total
4x Analog comparator, 1x 12-bit DAC
Full PMU Integration, DCDC+LDOs