Following peripherals are selected in the design.

Peripheral Selected

Quad SPI Flash
Enet 0
USB 0
SD 0
UART 1
Timer 0
GPIO

To see detailed information please follow below links:

MIO Configuration Table
Zynq Peripheral Configuration
DDR Configuration Information
SLCR settings

PLL Init Data
Clock Init Data
DDR Init Data
MIO Init Data

MIO configuration Table

MIO Pin	Peripheral	Signal	IO type	Speed	Pullup	Direction
MIO 0	GPIO	gpio[0]	LVCMOS 3.3V	slow	disabled	inout
MIO 1	Quad SPI Flash	qspi0_ss_b	LVCMOS 3.3V	fast	disabled	out
MIO 2	Quad SPI Flash	qspi0_io[0]	LVCMOS 3.3V	fast	disabled	inout
MIO 3	Quad SPI Flash	qspi0_io[1]	LVCMOS 3.3V	fast	disabled	inout
MIO 4	Quad SPI Flash	qspi0_io[2]	LVCMOS 3.3V	fast	disabled	inout
MIO 5	Quad SPI Flash	qspi0_io[3]	LVCMOS 3.3V	fast	disabled	inout
MIO 6	Quad SPI Flash	qspi0_sclk	LVCMOS 3.3V	fast	disabled	out
MIO 7	GPIO	gpio[7]	LVCMOS 3.3V	slow	disabled	out
MIO 8	Quad SPI Flash	qspi_fbclk	LVCMOS 3.3V	fast	disabled	out
MIO 9	GPIO	gpio[9]	LVCMOS 3.3V	slow	disabled	inout
MIO 10	GPIO	gpio[10]	LVCMOS 3.3V	slow	disabled	inout
MIO 11	GPIO	gpio[11]	LVCMOS 3.3V	slow	disabled	inout
MIO 12	GPIO	gpio[12]	LVCMOS 3.3V	slow	disabled	inout
MIO 13	GPIO	gpio[13]	LVCMOS 3.3V	slow	disabled	inout
MIO 14	GPIO	gpio[14]	LVCMOS 3.3V	slow	disabled	inout
MIO 15	GPIO	gpio[15]	LVCMOS 3.3V	slow	disabled	inout
MIO 16	Enet 0	tx_clk	LVCMOS 1.8V	fast	disabled	out
MIO 17	Enet 0	txd[0]	LVCMOS 1.8V	fast	disabled	out
MIO 18	Enet 0	txd[1]	LVCMOS 1.8V	fast	disabled	out
MIO 19	Enet 0	txd[2]	LVCMOS 1.8V	fast	disabled	out
MIO 20	Enet 0	txd[3]	LVCMOS 1.8V	fast	disabled	out
MIO 21	Enet 0	tx_ctl	LVCMOS 1.8V	fast	disabled	out
MIO 22	Enet 0	rx_clk	LVCMOS 1.8V	fast	disabled	in
MIO 23	Enet 0	rxd[0]	LVCMOS 1.8V	fast	disabled	in
MIO 24	Enet 0	rxd[1]	LVCMOS 1.8V	fast	disabled	in
MIO 25	Enet 0	rxd[2]	LVCMOS 1.8V	fast	disabled	in
MIO 26	Enet 0	rxd[3]	LVCMOS 1.8V	fast	disabled	in
MIO 27	Enet 0	rx_ctl	LVCMOS 1.8V	fast	disabled	in
MIO 28	USB 0	data[4]	LVCMOS 1.8V	fast	disabled	inout
MIO 29	USB 0	dir	LVCMOS 1.8V	fast	disabled	in
MIO 30	USB 0	stp	LVCMOS 1.8V	fast	disabled	out
MIO 31	USB 0	nxt	LVCMOS 1.8V	fast	disabled	in
MIO 32	USB 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 33	USB 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 34	USB 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 35	USB 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 36	USB 0	clk	LVCMOS 1.8V	fast	disabled	in
MIO 37	USB 0	data[5]	LVCMOS 1.8V	fast	disabled	inout
MIO 38	USB 0	data[6]	LVCMOS 1.8V	fast	disabled	inout
MIO 39	USB 0	data[7]	LVCMOS 1.8V	fast	disabled	inout
MIO 40	SD 0	clk	LVCMOS 1.8V	fast	disabled	inout
MIO 41	SD 0	cmd	LVCMOS 1.8V	fast	disabled	inout
MIO 42	SD 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 43	SD 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 44	SD 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 45	SD 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 46	SD 0	wp	LVCMOS 1.8V	slow	disabled	in
MIO 47	SD 0	cd	LVCMOS 1.8V	slow	disabled	in
MIO 48	UART 1	tx	LVCMOS 1.8V	slow	disabled	out
MIO 49	UART 1	rx	LVCMOS 1.8V	slow	disabled	in
MIO 50	GPIO	gpio[50]	LVCMOS 1.8V	slow	disabled	in
MIO 51	GPIO	gpio[51]	LVCMOS 1.8V	slow	disabled	in
MIO 52	Enet 0	mdc	LVCMOS 1.8V	slow	disabled	out
MIO 53	Enet 0	mdio	LVCMOS 1.8V	slow	disabled	inout

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Zynq Peripheral Configuration

Peripheral	Signal Group	Signal	MIO
Quad SPI Flash			MIO 1 .. 6
	Dual Quad SPI (4 bit)		Disabled
	Dual Quad SPI (Parallel 8 bit)		Disabled
	Feedback Clk		MIO 8
SRAM/NOR Flash			Disabled
NAND Flash			Disabled
Enet 0			MIO 16 .. 27
		tx_clk	MIO 16
		txd[3]	MIO 20
		txd[2]	MIO 19
		txd[1]	MIO 18
		txd[0]	MIO 17
		tx_ctl	MIO 21
		rx_clk	MIO 22
		rxd[3]	MIO 26
		rxd[2]	MIO 25
		rxd[1]	MIO 24
		rxd[0]	MIO 23
		rx_ctl	MIO 27
	MDIO		MIO 52 .. 53
		mdc	MIO 52
		mdio	MIO 53
Enet 1			Disabled
USB 0			MIO 28 .. 39
		clk	MIO 36
		dir	MIO 29
		stp	MIO 30
		nxt	MIO 31
		data[0]	MIO 32
		data[1]	MIO 33
		data[2]	MIO 34
		data[3]	MIO 35
		data[4]	MIO 28
		data[5]	MIO 37
		data[6]	MIO 38
		data[7]	MIO 39
USB 1			Disabled
SD 0			MIO 40 .. 45
	CD		MIO 47
	WP		MIO 46
	Power		Disabled
SD 1			Disabled
UART 0			Disabled
UART 1			MIO 48 .. 49
		rx	MIO 49
		tx	MIO 48
	Modem Signals		Disabled
I2C 0			Disabled
I2C 1			Disabled
SPI 0			Disabled
SPI 1			Disabled
CAN 0			Disabled
CAN 1			Disabled
Trace			Disabled
Timer 0			EMIO
		clk_in	EMIO
		wave_out	EMIO
Timer 1			Disabled
Watchdog			Disabled
PJTAG			Disabled
GPIO			MIO
Mode			Disabled
VCfg			Disabled

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DDR Memory information

DDR Controller Configuration

Parameter	Value
Enable DDR	1
Memory Type	DDR 3
Memory Part	MT41J128M16 HA-15E
DRAM bus width	32 Bit
ECC	Disabled
BURST Length (lppdr only)	8
Internal Vref	1
Operating Frequency (MHz)	533.333313
HIGH temperature	Normal (0-85)

Memory Part Configuration

Parameter	Value
DRAM IC bus width	16 Bits
DRAM Device Capacity	2048 MBits
Speed Bin	DDR3_1066F
BANK Address Count	3
ROW Address Count	14
COLUMN Address Count	10
CAS Latency	7
CAS Write Latency	6
RAS to CAS Delay	7
RECHARGE Time	7
tRC (ns )	49.5
tRASmin ( ns )	36.0
tFAW	45.0
ADDITIVE Latency	0

Training/Board Details

Parameter	Value
Write levelling	1
Read gate	1
Read data eye	1
DQS to Clock delay [0] (ns)	0.025
DQS to Clock delay [1] (ns)	0.028
DQS to Clock delay [2] (ns)	-0.009
DQS to Clock delay [3] (ns)	-0.061
Board delay [0] (ns)	0.41
Board delay [1] (ns)	0.411
Board delay [2] (ns)	0.341
Board delay [3] (ns)	0.358

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ps7_pll_init_data_1_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

Bitfield	Bits	Mask	Value	Shifted Value
UNLOCK_KEY	15:0	ffff	df0d	df0d
SLCR_UNLOCK @ 0XF8000008		ffff		df0d

PLL SLCR REGISTERS

ARM PLL INIT

Register : ARM_PLL_CFG @ 0XF8000110

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 fa fa000

ARM_PLL_CFG @ 0XF8000110 3ffff0 fa220

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RES	7:4	f0	2	20
PLL_CP	11:8	f00	2	200
LOCK_CNT	21:12	3ff000	fa	fa000
ARM_PLL_CFG @ 0XF8000110		3ffff0		fa220

UPDATE FB_DIV

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 28 28000

ARM_PLL_CTRL @ 0XF8000100 7f000 28000

Bitfield	Bits	Mask	Value	Shifted Value
PLL_FDIV	18:12	7f000	28	28000
ARM_PLL_CTRL @ 0XF8000100		7f000		28000

BY PASS PLL

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

ARM_PLL_CTRL @ 0XF8000100 10 10

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	1	10
ARM_PLL_CTRL @ 0XF8000100		10		10

ASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

ARM_PLL_CTRL @ 0XF8000100 1 1

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	1	1
ARM_PLL_CTRL @ 0XF8000100		1		1

DEASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

ARM_PLL_CTRL @ 0XF8000100 1 0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	0	0
ARM_PLL_CTRL @ 0XF8000100		1		0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

ARM_PLL_LOCK 0:0 1 1 1

PLL_STATUS @ 0XF800010C 1 1

Bitfield	Bits	Mask	Value	Shifted Value
ARM_PLL_LOCK	0:0	1	1	1
PLL_STATUS @ 0XF800010C		1		1

REMOVE PLL BY PASS

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

ARM_PLL_CTRL @ 0XF8000100 10 0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	0	0
ARM_PLL_CTRL @ 0XF8000100		10		0

Bitfield	Bits	Mask	Value	Shifted Value
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	2	200
CPU_6OR4XCLKACT	24:24	1000000	1	1000000
CPU_3OR2XCLKACT	25:25	2000000	1	2000000
CPU_2XCLKACT	26:26	4000000	1	4000000
CPU_1XCLKACT	27:27	8000000	1	8000000
CPU_PERI_CLKACT	28:28	10000000	1	10000000
ARM_CLK_CTRL @ 0XF8000120		1f003f30		1f000200

DDR PLL INIT

Register : DDR_PLL_CFG @ 0XF8000114

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 12c 12c000

DDR_PLL_CFG @ 0XF8000114 3ffff0 12c220

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RES	7:4	f0	2	20
PLL_CP	11:8	f00	2	200
LOCK_CNT	21:12	3ff000	12c	12c000
DDR_PLL_CFG @ 0XF8000114		3ffff0		12c220

UPDATE FB_DIV

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 20 20000

DDR_PLL_CTRL @ 0XF8000104 7f000 20000

Bitfield	Bits	Mask	Value	Shifted Value
PLL_FDIV	18:12	7f000	20	20000
DDR_PLL_CTRL @ 0XF8000104		7f000		20000

BY PASS PLL

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

DDR_PLL_CTRL @ 0XF8000104 10 10

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	1	10
DDR_PLL_CTRL @ 0XF8000104		10		10

ASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

DDR_PLL_CTRL @ 0XF8000104 1 1

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	1	1
DDR_PLL_CTRL @ 0XF8000104		1		1

DEASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

DDR_PLL_CTRL @ 0XF8000104 1 0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	0	0
DDR_PLL_CTRL @ 0XF8000104		1		0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

DDR_PLL_LOCK 1:1 2 1 2

PLL_STATUS @ 0XF800010C 2 2

Bitfield	Bits	Mask	Value	Shifted Value
DDR_PLL_LOCK	1:1	2	1	2
PLL_STATUS @ 0XF800010C		2		2

REMOVE PLL BY PASS

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

DDR_PLL_CTRL @ 0XF8000104 10 0

Register : DDR_CLK_CTRL @ 0XF8000124

Bitfield Bits Mask Value Shifted Value

DDR_3XCLKACT 0:0 1 1 1

DDR_2XCLKACT 1:1 2 1 2

DDR_3XCLK_DIVISOR 25:20 3f00000 2 200000

DDR_2XCLK_DIVISOR 31:26 fc000000 3 c000000

DDR_CLK_CTRL @ 0XF8000124 fff00003 c200003

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	0	0
DDR_PLL_CTRL @ 0XF8000104		10		0

Bitfield	Bits	Mask	Value	Shifted Value
DDR_3XCLKACT	0:0	1	1	1
DDR_2XCLKACT	1:1	2	1	2
DDR_3XCLK_DIVISOR	25:20	3f00000	2	200000
DDR_2XCLK_DIVISOR	31:26	fc000000	3	c000000
DDR_CLK_CTRL @ 0XF8000124		fff00003		c200003

IO PLL INIT

Register : IO_PLL_CFG @ 0XF8000118

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 c c0

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 145 145000

IO_PLL_CFG @ 0XF8000118 3ffff0 1452c0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RES	7:4	f0	c	c0
PLL_CP	11:8	f00	2	200
LOCK_CNT	21:12	3ff000	145	145000
IO_PLL_CFG @ 0XF8000118		3ffff0		1452c0

UPDATE FB_DIV

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 1e 1e000

IO_PLL_CTRL @ 0XF8000108 7f000 1e000

Bitfield	Bits	Mask	Value	Shifted Value
PLL_FDIV	18:12	7f000	1e	1e000
IO_PLL_CTRL @ 0XF8000108		7f000		1e000

BY PASS PLL

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

IO_PLL_CTRL @ 0XF8000108 10 10

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	1	10
IO_PLL_CTRL @ 0XF8000108		10		10

ASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

IO_PLL_CTRL @ 0XF8000108 1 1

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	1	1
IO_PLL_CTRL @ 0XF8000108		1		1

DEASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

IO_PLL_CTRL @ 0XF8000108 1 0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_RESET	0:0	1	0	0
IO_PLL_CTRL @ 0XF8000108		1		0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

IO_PLL_LOCK 2:2 4 1 4

PLL_STATUS @ 0XF800010C 4 4

Bitfield	Bits	Mask	Value	Shifted Value
IO_PLL_LOCK	2:2	4	1	4
PLL_STATUS @ 0XF800010C		4		4

REMOVE PLL BY PASS

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

IO_PLL_CTRL @ 0XF8000108 10 0

Bitfield	Bits	Mask	Value	Shifted Value
PLL_BYPASS_FORCE	4:4	10	0	0
IO_PLL_CTRL @ 0XF8000108		10		0

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

Bitfield	Bits	Mask	Value	Shifted Value
LOCK_KEY	15:0	ffff	767b	767b
SLCR_LOCK @ 0XF8000004		ffff		767b

ps7_clock_init_data_1_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

Bitfield	Bits	Mask	Value	Shifted Value
UNLOCK_KEY	15:0	ffff	df0d	df0d
SLCR_UNLOCK @ 0XF8000008		ffff		df0d

CLOCK CONTROL SLCR REGISTERS

Register : DCI_CLK_CTRL @ 0XF8000128

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

DIVISOR0 13:8 3f00 23 2300

DIVISOR1 25:20 3f00000 3 300000

DCI_CLK_CTRL @ 0XF8000128 3f03f01 302301
Register : GEM0_RCLK_CTRL @ 0XF8000138

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 4:4 10 0 0

GEM0_RCLK_CTRL @ 0XF8000138 11 1
Register : GEM0_CLK_CTRL @ 0XF8000140

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 6:4 70 0 0

DIVISOR 13:8 3f00 8 800

DIVISOR1 25:20 3f00000 1 100000

GEM0_CLK_CTRL @ 0XF8000140 3f03f71 100801
Register : LQSPI_CLK_CTRL @ 0XF800014C

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

LQSPI_CLK_CTRL @ 0XF800014C 3f31 501
Register : SDIO_CLK_CTRL @ 0XF8000150

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 1 1

CLKACT1 1:1 2 0 0

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

SDIO_CLK_CTRL @ 0XF8000150 3f33 1401
Register : UART_CLK_CTRL @ 0XF8000154

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 0 0

CLKACT1 1:1 2 1 2

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

UART_CLK_CTRL @ 0XF8000154 3f33 1402
Register : PCAP_CLK_CTRL @ 0XF8000168

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

PCAP_CLK_CTRL @ 0XF8000168 3f31 501
Register : FPGA0_CLK_CTRL @ 0XF8000170

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 a a00

DIVISOR1 25:20 3f00000 1 100000

FPGA0_CLK_CTRL @ 0XF8000170 3f03f30 100a00
Register : FPGA1_CLK_CTRL @ 0XF8000180

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 7 700

DIVISOR1 25:20 3f00000 1 100000

FPGA1_CLK_CTRL @ 0XF8000180 3f03f30 100700
Register : FPGA2_CLK_CTRL @ 0XF8000190

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA2_CLK_CTRL @ 0XF8000190 3f03f30 101400
Register : FPGA3_CLK_CTRL @ 0XF80001A0

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA3_CLK_CTRL @ 0XF80001A0 3f03f30 101400
Register : CLK_621_TRUE @ 0XF80001C4

Bitfield Bits Mask Value Shifted Value

CLK_621_TRUE 0:0 1 1 1

CLK_621_TRUE @ 0XF80001C4 1 1

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT	0:0	1	1	1
DIVISOR0	13:8	3f00	23	2300
DIVISOR1	25:20	3f00000	3	300000
DCI_CLK_CTRL @ 0XF8000128		3f03f01		302301

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT	0:0	1	1	1
SRCSEL	4:4	10	0	0
GEM0_RCLK_CTRL @ 0XF8000138		11		1

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT	0:0	1	1	1
SRCSEL	6:4	70	0	0
DIVISOR	13:8	3f00	8	800
DIVISOR1	25:20	3f00000	1	100000
GEM0_CLK_CTRL @ 0XF8000140		3f03f71		100801

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT	0:0	1	1	1
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	5	500
LQSPI_CLK_CTRL @ 0XF800014C		3f31		501

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT0	0:0	1	1	1
CLKACT1	1:1	2	0	0
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	14	1400
SDIO_CLK_CTRL @ 0XF8000150		3f33		1401

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT0	0:0	1	0	0
CLKACT1	1:1	2	1	2
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	14	1400
UART_CLK_CTRL @ 0XF8000154		3f33		1402

Bitfield	Bits	Mask	Value	Shifted Value
CLKACT	0:0	1	1	1
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	5	500
PCAP_CLK_CTRL @ 0XF8000168		3f31		501

Bitfield	Bits	Mask	Value	Shifted Value
CLK_621_TRUE	0:0	1	1	1
CLK_621_TRUE @ 0XF80001C4		1		1

Bitfield	Bits	Mask	Value	Shifted Value
DMA_CPU_2XCLKACT	0:0	1	1	1
USB0_CPU_1XCLKACT	2:2	4	1	4
USB1_CPU_1XCLKACT	3:3	8	1	8
GEM0_CPU_1XCLKACT	6:6	40	1	40
GEM1_CPU_1XCLKACT	7:7	80	0	0
SDI0_CPU_1XCLKACT	10:10	400	1	400
SDI1_CPU_1XCLKACT	11:11	800	0	0
SPI0_CPU_1XCLKACT	14:14	4000	0	0
SPI1_CPU_1XCLKACT	15:15	8000	0	0
CAN0_CPU_1XCLKACT	16:16	10000	0	0
CAN1_CPU_1XCLKACT	17:17	20000	0	0
I2C0_CPU_1XCLKACT	18:18	40000	1	40000
I2C1_CPU_1XCLKACT	19:19	80000	1	80000
UART0_CPU_1XCLKACT	20:20	100000	0	0
UART1_CPU_1XCLKACT	21:21	200000	1	200000
GPIO_CPU_1XCLKACT	22:22	400000	1	400000
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000
APER_CLK_CTRL @ 0XF800012C		1ffcccd		1ec044d

THIS SHOULD BE BLANK

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

Bitfield	Bits	Mask	Value	Shifted Value
LOCK_KEY	15:0	ffff	767b	767b
SLCR_LOCK @ 0XF8000004		ffff		767b

ps7_ddr_init_data_1_0

DDR INITIALIZATION

LOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	0	0
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		80

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_rfc_nom_x32	11:0	fff	81	81
reg_ddrc_active_ranks	13:12	3000	1	1000
reg_ddrc_addrmap_cs_bit0	18:14	7c000	0	0
reg_ddrc_wr_odt_block	20:19	180000	1	80000
reg_ddrc_diff_rank_rd_2cycle_gap	21:21	200000	0	0
reg_ddrc_addrmap_cs_bit1	26:22	7c00000	0	0
reg_ddrc_addrmap_open_bank	27:27	8000000	0	0
reg_ddrc_addrmap_4bank_ram	28:28	10000000	0	0
Two_rank_cfg @ 0XF8006004		1fffffff		81081

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_hpr_min_non_critical_x32	10:0	7ff	f	f
reg_ddrc_hpr_max_starve_x32	21:11	3ff800	f	7800
reg_ddrc_hpr_xact_run_length	25:22	3c00000	f	3c00000
HPR_reg @ 0XF8006008		3ffffff		3c0780f

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_lpr_min_non_critical_x32	10:0	7ff	1	1
reg_ddrc_lpr_max_starve_x32	21:11	3ff800	2	1000
reg_ddrc_lpr_xact_run_length	25:22	3c00000	8	2000000
LPR_reg @ 0XF800600C		3ffffff		2001001

Register : WR_reg @ 0XF8006010

Bitfield Bits Mask Value Shifted Value

reg_ddrc_w_min_non_critical_x32 10:0 7ff 1 1

reg_ddrc_w_xact_run_length 14:11 7800 8 4000

reg_ddrc_w_max_starve_x32 25:15 3ff8000 2 10000

WR_reg @ 0XF8006010 3ffffff 14001
Register : DRAM_param_reg0 @ 0XF8006014

Bitfield Bits Mask Value Shifted Value

reg_ddrc_t_rc 5:0 3f 1b 1b

reg_ddrc_t_rfc_min 13:6 3fc0 56 1580

reg_ddrc_post_selfref_gap_x32 20:14 1fc000 10 40000

DRAM_param_reg0 @ 0XF8006014 1fffff 4159b

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_w_min_non_critical_x32	10:0	7ff	1	1
reg_ddrc_w_xact_run_length	14:11	7800	8	4000
reg_ddrc_w_max_starve_x32	25:15	3ff8000	2	10000
WR_reg @ 0XF8006010		3ffffff		14001

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_wr2pre	4:0	1f	12	12
reg_ddrc_powerdown_to_x32	9:5	3e0	6	c0
reg_ddrc_t_faw	15:10	fc00	18	6000
reg_ddrc_t_ras_max	21:16	3f0000	24	240000
reg_ddrc_t_ras_min	26:22	7c00000	14	5000000
reg_ddrc_t_cke	31:28	f0000000	4	40000000
DRAM_param_reg1 @ 0XF8006018		f7ffffff		452460d2

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_write_latency	4:0	1f	5	5
reg_ddrc_rd2wr	9:5	3e0	7	e0
reg_ddrc_wr2rd	14:10	7c00	e	3800
reg_ddrc_t_xp	19:15	f8000	4	20000
reg_ddrc_pad_pd	22:20	700000	0	0
reg_ddrc_rd2pre	27:23	f800000	4	2000000
reg_ddrc_t_rcd	31:28	f0000000	7	70000000
DRAM_param_reg2 @ 0XF800601C		ffffffff		720238e5

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_ccd	4:2	1c	4	10
reg_ddrc_t_rrd	7:5	e0	6	c0
reg_ddrc_refresh_margin	11:8	f00	2	200
reg_ddrc_t_rp	15:12	f000	7	7000
reg_ddrc_refresh_to_x32	20:16	1f0000	8	80000
reg_ddrc_sdram	21:21	200000	1	200000
reg_ddrc_mobile	22:22	400000	0	0
reg_ddrc_clock_stop_en	23:23	800000	0	0
reg_ddrc_read_latency	28:24	1f000000	7	7000000
reg_phy_mode_ddr1_ddr2	29:29	20000000	1	20000000
reg_ddrc_dis_pad_pd	30:30	40000000	0	0
reg_ddrc_loopback	31:31	80000000	0	0
DRAM_param_reg3 @ 0XF8006020		fffffffc		272872d0

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_en_2t_timing_mode	0:0	1	0	0
reg_ddrc_prefer_write	1:1	2	0	0
reg_ddrc_max_rank_rd	5:2	3c	f	3c
reg_ddrc_mr_wr	6:6	40	0	0
reg_ddrc_mr_addr	8:7	180	0	0
reg_ddrc_mr_data	24:9	1fffe00	0	0
ddrc_reg_mr_wr_busy	25:25	2000000	0	0
reg_ddrc_mr_type	26:26	4000000	0	0
reg_ddrc_mr_rdata_valid	27:27	8000000	0	0
DRAM_param_reg4 @ 0XF8006024		fffffff		3c

Register : DRAM_init_param @ 0XF8006028

Bitfield Bits Mask Value Shifted Value

reg_ddrc_final_wait_x32 6:0 7f 7 7

reg_ddrc_pre_ocd_x32 10:7 780 0 0

reg_ddrc_t_mrd 13:11 3800 4 2000

DRAM_init_param @ 0XF8006028 3fff 2007
Register : DRAM_EMR_reg @ 0XF800602C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_emr2 15:0 ffff 8 8

reg_ddrc_emr3 31:16 ffff0000 0 0

DRAM_EMR_reg @ 0XF800602C ffffffff 8
Register : DRAM_EMR_MR_reg @ 0XF8006030

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr 15:0 ffff 930 930

reg_ddrc_emr 31:16 ffff0000 4 40000

DRAM_EMR_MR_reg @ 0XF8006030 ffffffff 40930

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_burst_rdwr	3:0	f	4	4
reg_ddrc_pre_cke_x1024	13:4	3ff0	69	690
reg_ddrc_post_cke_x1024	25:16	3ff0000	1	10000
reg_ddrc_burstchop	28:28	10000000	0	0
DRAM_burst8_rdwr @ 0XF8006034		13ff3fff		10694

Bitfield	Bits	Mask	Value
reg_ddrc_force_low_pri_n	0:0	1	0
reg_ddrc_dis_dq	1:1	2	0
reg_phy_debug_mode	6:6	40	0
reg_phy_wr_level_start	7:7	80	0
reg_phy_rd_level_start	8:8	100	0
reg_phy_dq0_wait_t	12:9	1e00	0
DRAM_disable_DQ @ 0XF8006038		1fc3

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_bank_b0	3:0	f	7	7
reg_ddrc_addrmap_bank_b1	7:4	f0	7	70
reg_ddrc_addrmap_bank_b2	11:8	f00	7	700
reg_ddrc_addrmap_col_b5	15:12	f000	0	0
reg_ddrc_addrmap_col_b6	19:16	f0000	0	0
DRAM_addr_map_bank @ 0XF800603C		fffff		777

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_col_b2	3:0	f	0	0
reg_ddrc_addrmap_col_b3	7:4	f0	0	0
reg_ddrc_addrmap_col_b4	11:8	f00	0	0
reg_ddrc_addrmap_col_b7	15:12	f000	0	0
reg_ddrc_addrmap_col_b8	19:16	f0000	0	0
reg_ddrc_addrmap_col_b9	23:20	f00000	f	f00000
reg_ddrc_addrmap_col_b10	27:24	f000000	f	f000000
reg_ddrc_addrmap_col_b11	31:28	f0000000	f	f0000000
DRAM_addr_map_col @ 0XF8006040		ffffffff		fff00000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_row_b0	3:0	f	6	6
reg_ddrc_addrmap_row_b1	7:4	f0	6	60
reg_ddrc_addrmap_row_b2_11	11:8	f00	6	600
reg_ddrc_addrmap_row_b12	15:12	f000	6	6000
reg_ddrc_addrmap_row_b13	19:16	f0000	6	60000
reg_ddrc_addrmap_row_b14	23:20	f00000	f	f00000
reg_ddrc_addrmap_row_b15	27:24	f000000	f	f000000
DRAM_addr_map_row @ 0XF8006044		fffffff		ff66666

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_rank0_rd_odt	2:0	7	0	0
reg_ddrc_rank0_wr_odt	5:3	38	1	8
reg_ddrc_rank1_rd_odt	8:6	1c0	1	40
reg_ddrc_rank1_wr_odt	11:9	e00	1	200
reg_phy_rd_local_odt	13:12	3000	0	0
reg_phy_wr_local_odt	15:14	c000	3	c000
reg_phy_idle_local_odt	17:16	30000	3	30000
reg_ddrc_rank2_rd_odt	20:18	1c0000	0	0
reg_ddrc_rank2_wr_odt	23:21	e00000	0	0
reg_ddrc_rank3_rd_odt	26:24	7000000	0	0
reg_ddrc_rank3_wr_odt	29:27	38000000	0	0
DRAM_ODT_reg @ 0XF8006048		3fffffff		3c248

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_rd_cmd_to_data	3:0	f	0	0
reg_phy_wr_cmd_to_data	7:4	f0	0	0
reg_phy_rdc_we_to_re_delay	11:8	f00	8	800
reg_phy_rdc_fifo_rst_disable	15:15	8000	0	0
reg_phy_use_fixed_re	16:16	10000	1	10000
reg_phy_rdc_fifo_rst_err_cnt_clr	17:17	20000	0	0
reg_phy_dis_phy_ctrl_rstn	18:18	40000	0	0
reg_phy_clk_stall_level	19:19	80000	0	0
reg_phy_gatelvl_num_of_dq0	27:24	f000000	7	7000000
reg_phy_wrlvl_num_of_dq0	31:28	f0000000	7	70000000
phy_cmd_timeout_rddata_cpt @ 0XF8006050		ff0f8fff		77010800

Register : DLL_calib @ 0XF8006058

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dll_calib_to_min_x1024 7:0 ff 1 1

reg_ddrc_dll_calib_to_max_x1024 15:8 ff00 1 100

reg_ddrc_dis_dll_calib 16:16 10000 0 0

DLL_calib @ 0XF8006058 1ffff 101
Register : ODT_delay_hold @ 0XF800605C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_rd_odt_delay 3:0 f 3 3

reg_ddrc_wr_odt_delay 7:4 f0 0 0

reg_ddrc_rd_odt_hold 11:8 f00 0 0

reg_ddrc_wr_odt_hold 15:12 f000 5 5000

ODT_delay_hold @ 0XF800605C ffff 5003

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_pageclose	0:0	1	0	0
reg_ddrc_lpr_num_entries	6:1	7e	1f	3e
reg_ddrc_auto_pre_en	7:7	80	0	0
reg_ddrc_refresh_update_level	8:8	100	0	0
reg_ddrc_dis_wc	9:9	200	0	0
reg_ddrc_dis_collision_page_opt	10:10	400	0	0
reg_ddrc_selfref_en	12:12	1000	0	0
ctrl_reg1 @ 0XF8006060		17ff		3e

Register : ctrl_reg2 @ 0XF8006064

Bitfield Bits Mask Value Shifted Value

reg_ddrc_go2critical_hysteresis 12:5 1fe0 0 0

reg_arb_go2critical_en 17:17 20000 1 20000

ctrl_reg2 @ 0XF8006064 21fe0 20000
Register : ctrl_reg3 @ 0XF8006068

Bitfield Bits Mask Value Shifted Value

reg_ddrc_wrlvl_ww 7:0 ff 41 41

reg_ddrc_rdlvl_rr 15:8 ff00 41 4100

reg_ddrc_dfi_t_wlmrd 25:16 3ff0000 28 280000

ctrl_reg3 @ 0XF8006068 3ffffff 284141
Register : ctrl_reg4 @ 0XF800606C

Bitfield Bits Mask Value Shifted Value

dfi_t_ctrlupd_interval_min_x1024 7:0 ff 10 10

dfi_t_ctrlupd_interval_max_x1024 15:8 ff00 16 1600

ctrl_reg4 @ 0XF800606C ffff 1610
Register : CHE_REFRESH_TIMER01 @ 0XF80060A0

Bitfield Bits Mask Value Shifted Value

refresh_timer0_start_value_x32 11:0 fff 0 0

refresh_timer1_start_value_x32 23:12 fff000 8 8000

CHE_REFRESH_TIMER01 @ 0XF80060A0 ffffff 8000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dis_auto_zq	0:0	1	0	0
reg_ddrc_ddr3	1:1	2	1	2
reg_ddrc_t_mod	11:2	ffc	200	800
reg_ddrc_t_zq_long_nop	21:12	3ff000	200	200000
reg_ddrc_t_zq_short_nop	31:22	ffc00000	40	10000000
CHE_T_ZQ @ 0XF80060A4		ffffffff		10200802

Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8

Bitfield Bits Mask Value Shifted Value

t_zq_short_interval_x1024 19:0 fffff cb73 cb73

dram_rstn_x1024 27:20 ff00000 69 6900000

CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8 fffffff 690cb73
Register : deep_pwrdwn_reg @ 0XF80060AC

Bitfield Bits Mask Value Shifted Value

deeppowerdown_en 0:0 1 0 0

deeppowerdown_to_x1024 8:1 1fe ff 1fe

deep_pwrdwn_reg @ 0XF80060AC 1ff 1fe

Bitfield	Bits	Mask	Value	Shifted Value
dfi_wrlvl_max_x1024	11:0	fff	fff	fff
dfi_rdlvl_max_x1024	23:12	fff000	fff	fff000
ddrc_reg_twrlvl_max_error	24:24	1000000	0	0
ddrc_reg_trdlvl_max_error	25:25	2000000	0	0
reg_ddrc_dfi_wr_level_en	26:26	4000000	1	4000000
reg_ddrc_dfi_rd_dqs_gate_level	27:27	8000000	1	8000000
reg_ddrc_dfi_rd_data_eye_train	28:28	10000000	1	10000000
reg_2c @ 0XF80060B0		1fffffff		1cffffff

Register : reg_2d @ 0XF80060B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_2t_delay 8:0 1ff 0 0

reg_ddrc_skip_ocd 9:9 200 1 200

reg_ddrc_dis_pre_bypass 10:10 400 0 0

reg_2d @ 0XF80060B4 7ff 200
Register : dfi_timing @ 0XF80060B8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dfi_t_rddata_en 4:0 1f 6 6

reg_ddrc_dfi_t_ctrlup_min 14:5 7fe0 3 60

reg_ddrc_dfi_t_ctrlup_max 24:15 1ff8000 40 200000

dfi_timing @ 0XF80060B8 1ffffff 200066
Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4

Bitfield Bits Mask Value Shifted Value

Clear_Uncorrectable_DRAM_ECC_error 0:0 1 0 0

Clear_Correctable_DRAM_ECC_error 1:1 2 0 0

CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4 3 0
Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8

Bitfield Bits Mask Value Shifted Value

CORR_ECC_LOG_VALID 0:0 1 0 0

ECC_CORRECTED_BIT_NUM 7:1 fe 0 0

CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8 ff 0
Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC

Bitfield Bits Mask Value Shifted Value

UNCORR_ECC_LOG_VALID 0:0 1 0 0

CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC 1 0
Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0

Bitfield Bits Mask Value Shifted Value

STAT_NUM_CORR_ERR 15:8 ff00 0 0

STAT_NUM_UNCORR_ERR 7:0 ff 0 0

CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0 ffff 0
Register : ECC_scrub @ 0XF80060F4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_ecc_mode 2:0 7 0 0

reg_ddrc_dis_scrub 3:3 8 1 8

ECC_scrub @ 0XF80060F4 f 8
Register : phy_rcvr_enable @ 0XF8006114

Bitfield Bits Mask Value Shifted Value

reg_phy_dif_on 3:0 f 0 0

reg_phy_dif_off 7:4 f0 0 0

phy_rcvr_enable @ 0XF8006114 ff 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006118		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF800611C		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006120		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006124		7fffffff		40000001

Register : phy_init_ratio @ 0XF800612C

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 cf 33c00

phy_init_ratio @ 0XF800612C fffff 33c03
Register : phy_init_ratio @ 0XF8006130

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 d0 34000

phy_init_ratio @ 0XF8006130 fffff 34003
Register : phy_init_ratio @ 0XF8006134

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 bd 2f400

phy_init_ratio @ 0XF8006134 fffff 2f400
Register : phy_init_ratio @ 0XF8006138

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 c1 30400

phy_init_ratio @ 0XF8006138 fffff 30400
Register : phy_rd_dqs_cfg @ 0XF8006140

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006140 fffff 35
Register : phy_rd_dqs_cfg @ 0XF8006144

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006144 fffff 35
Register : phy_rd_dqs_cfg @ 0XF8006148

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006148 fffff 35
Register : phy_rd_dqs_cfg @ 0XF800614C

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF800614C fffff 35
Register : phy_wr_dqs_cfg @ 0XF8006154

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006154 fffff 83
Register : phy_wr_dqs_cfg @ 0XF8006158

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006158 fffff 83
Register : phy_wr_dqs_cfg @ 0XF800615C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 7f 7f

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF800615C fffff 7f
Register : phy_wr_dqs_cfg @ 0XF8006160

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 78 78

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006160 fffff 78
Register : phy_we_cfg @ 0XF8006168

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 124 124

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006168 1fffff 124
Register : phy_we_cfg @ 0XF800616C

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 125 125

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF800616C 1fffff 125
Register : phy_we_cfg @ 0XF8006170

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 112 112

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006170 1fffff 112
Register : phy_we_cfg @ 0XF8006174

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 116 116

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006174 1fffff 116
Register : wr_data_slv @ 0XF800617C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF800617C fffff c3
Register : wr_data_slv @ 0XF8006180

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006180 fffff c3
Register : wr_data_slv @ 0XF8006184

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff bf bf

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006184 fffff bf
Register : wr_data_slv @ 0XF8006188

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff b8 b8

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006188 fffff b8

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_loopback	0:0	1	0	0
reg_phy_bl2	1:1	2	0	0
reg_phy_at_spd_atpg	2:2	4	0	0
reg_phy_bist_enable	3:3	8	0	0
reg_phy_bist_force_err	4:4	10	0	0
reg_phy_bist_mode	6:5	60	0	0
reg_phy_invert_clkout	7:7	80	1	80
reg_phy_all_dq_mpr_rd_resp	8:8	100	0	0
reg_phy_sel_logic	9:9	200	0	0
reg_phy_ctrl_slave_ratio	19:10	ffc00	100	40000
reg_phy_ctrl_slave_force	20:20	100000	0	0
reg_phy_ctrl_slave_delay	27:21	fe00000	0	0
reg_phy_use_rank0_delays	28:28	10000000	1	10000000
reg_phy_lpddr	29:29	20000000	0	0
reg_phy_cmd_latency	30:30	40000000	0	0
reg_phy_int_lpbk	31:31	80000000	0	0
reg_64 @ 0XF8006190		ffffffff		10040080

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wr_rl_delay	4:0	1f	2	2
reg_phy_rd_rl_delay	9:5	3e0	4	80
reg_phy_dll_lock_diff	13:10	3c00	f	3c00
reg_phy_use_wr_level	14:14	4000	1	4000
reg_phy_use_rd_dqs_gate_level	15:15	8000	1	8000
reg_phy_use_rd_data_eye_level	16:16	10000	1	10000
reg_phy_dis_calib_rst	17:17	20000	0	0
reg_phy_ctrl_slave_delay	19:18	c0000	0	0
reg_65 @ 0XF8006194		fffff		1fc82

Register : page_mask @ 0XF8006204

Bitfield Bits Mask Value Shifted Value

reg_arb_page_addr_mask 31:0 0 0 0

page_mask @ 0XF8006204 0 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port @ 0XF8006208		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port @ 0XF800620C		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port @ 0XF8006210		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port @ 0XF8006214		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006218		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF800621C		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006220		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006224		f03ff		3ff

Register : lpddr_ctrl0 @ 0XF80062A8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_lpddr2 0:0 1 0 0

reg_ddrc_per_bank_refresh 1:1 2 0 0

reg_ddrc_derate_enable 2:2 4 0 0

reg_ddrc_mr4_margin 11:4 ff0 0 0

lpddr_ctrl0 @ 0XF80062A8 ff7 0
Register : lpddr_ctrl1 @ 0XF80062AC

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr4_read_interval 31:0 0 0 0

lpddr_ctrl1 @ 0XF80062AC 0 0
Register : lpddr_ctrl2 @ 0XF80062B0

Bitfield Bits Mask Value Shifted Value

reg_ddrc_min_stable_clock_x1 3:0 f 5 5

reg_ddrc_idle_after_reset_x32 11:4 ff0 12 120

reg_ddrc_t_mrw 21:12 3ff000 5 5000

lpddr_ctrl2 @ 0XF80062B0 3fffff 5125
Register : lpddr_ctrl3 @ 0XF80062B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_max_auto_init_x1024 7:0 ff a8 a8

reg_ddrc_dev_zqinit_x32 17:8 3ff00 12 1200

lpddr_ctrl3 @ 0XF80062B4 3ffff 12a8

POLL ON DCI STATUS

Register : DDRIOB_DCI_STATUS @ 0XF8000B74

Bitfield Bits Mask Value Shifted Value

DONE 13:13 2000 1 2000

DDRIOB_DCI_STATUS @ 0XF8000B74 2000 2000

UNLOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	1	1
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		81

CHECK DDR STATUS

Register : mode_sts_reg @ 0XF8006054

Bitfield Bits Mask Value Shifted Value

ddrc_reg_operating_mode 2:0 7 1 1

mode_sts_reg @ 0XF8006054 7 1

ps7_mio_init_data_1_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

OCM REMAPPING

DDRIOB SETTINGS

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR0 @ 0XF8000B40		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR1 @ 0XF8000B44		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	1	2
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA0 @ 0XF8000B48		fff		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	1	2
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA1 @ 0XF8000B4C		fff		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	2	4
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF0 @ 0XF8000B50		fff		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	2	4
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF1 @ 0XF8000B54		fff		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_CLOCK @ 0XF8000B58		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	1a	68000
SLEW_N	23:19	f80000	1a	d00000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C		ffffffff		d6861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	6	18000
SLEW_N	23:19	f80000	1f	f80000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60		ffffffff		f9861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	6	18000
SLEW_N	23:19	f80000	1f	f80000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64		ffffffff		f9861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	1a	68000
SLEW_N	23:19	f80000	1a	d00000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68		ffffffff		d6861c

Bitfield	Bits	Mask	Value	Shifted Value
VREF_INT_EN	0:0	1	1	1
VREF_SEL	4:1	1e	4	8
VREF_EXT_EN	6:5	60	0	0
VREF_PULLUP_EN	8:7	180	0	0
REFIO_EN	9:9	200	1	200
REFIO_PULLUP_EN	12:12	1000	0	0
DRST_B_PULLUP_EN	13:13	2000	0	0
CKE_PULLUP_EN	14:14	4000	0	0
DDRIOB_DDR_CTRL @ 0XF8000B6C		73ff		209

ASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 1 1

VRN_OUT 5:5 20 1 20

DDRIOB_DCI_CTRL @ 0XF8000B70 21 21

DEASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 0 0

VRN_OUT 5:5 20 1 20

DDRIOB_DCI_CTRL @ 0XF8000B70 21 20

Bitfield	Bits	Mask	Value	Shifted Value
RESET	0:0	1	1	1
ENABLE	1:1	2	1	2
VRP_TRI	2:2	4	0	0
VRN_TRI	3:3	8	0	0
VRP_OUT	4:4	10	0	0
VRN_OUT	5:5	20	1	20
NREF_OPT1	7:6	c0	0	0
NREF_OPT2	10:8	700	0	0
NREF_OPT4	13:11	3800	1	800
PREF_OPT1	16:14	1c000	0	0
PREF_OPT2	19:17	e0000	0	0
UPDATE_CONTROL	20:20	100000	0	0
INIT_COMPLETE	21:21	200000	0	0
TST_CLK	22:22	400000	0	0
TST_HLN	23:23	800000	0	0
TST_HLP	24:24	1000000	0	0
TST_RST	25:25	2000000	0	0
INT_DCI_EN	26:26	4000000	0	0
DDRIOB_DCI_CTRL @ 0XF8000B70		7ffffff		823

MIO PROGRAMMING

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_00 @ 0XF8000700		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_01 @ 0XF8000704		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_02 @ 0XF8000708		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_03 @ 0XF800070C		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_04 @ 0XF8000710		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_05 @ 0XF8000714		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_06 @ 0XF8000718		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_07 @ 0XF800071C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_08 @ 0XF8000720		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_09 @ 0XF8000724		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_10 @ 0XF8000728		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_11 @ 0XF800072C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_12 @ 0XF8000730		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_13 @ 0XF8000734		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_14 @ 0XF8000738		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_15 @ 0XF800073C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_16 @ 0XF8000740		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_17 @ 0XF8000744		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_18 @ 0XF8000748		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_19 @ 0XF800074C		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_20 @ 0XF8000750		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_21 @ 0XF8000754		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_22 @ 0XF8000758		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_23 @ 0XF800075C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_24 @ 0XF8000760		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_25 @ 0XF8000764		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_26 @ 0XF8000768		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_27 @ 0XF800076C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_28 @ 0XF8000770		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_29 @ 0XF8000774		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_30 @ 0XF8000778		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_31 @ 0XF800077C		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_32 @ 0XF8000780		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_33 @ 0XF8000784		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_34 @ 0XF8000788		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_35 @ 0XF800078C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_36 @ 0XF8000790		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_37 @ 0XF8000794		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_38 @ 0XF8000798		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_39 @ 0XF800079C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_40 @ 0XF80007A0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_41 @ 0XF80007A4		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_42 @ 0XF80007A8		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_43 @ 0XF80007AC		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_44 @ 0XF80007B0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_45 @ 0XF80007B4		3fff		380

Register : MIO_PIN_46 @ 0XF80007B8

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_46 @ 0XF80007B8 3f01 201
Register : MIO_PIN_47 @ 0XF80007BC

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_47 @ 0XF80007BC 3f01 201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_48 @ 0XF80007C0		3fff		2e0

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_49 @ 0XF80007C4		3fff		2e1

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_50 @ 0XF80007C8		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_51 @ 0XF80007CC		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_52 @ 0XF80007D0		3fff		280

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_53 @ 0XF80007D4		3fff		280

Register : SD0_WP_CD_SEL @ 0XF8000830

Bitfield Bits Mask Value Shifted Value

SDIO0_WP_SEL 5:0 3f 2e 2e

SDIO0_CD_SEL 21:16 3f0000 2f 2f0000

SD0_WP_CD_SEL @ 0XF8000830 3f003f 2f002e

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_peripherals_init_data_1_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register : DDRIOB_DATA0 @ 0XF8000B48

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA0 @ 0XF8000B48 180 180
Register : DDRIOB_DATA1 @ 0XF8000B4C

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA1 @ 0XF8000B4C 180 180
Register : DDRIOB_DIFF0 @ 0XF8000B50

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF0 @ 0XF8000B50 180 180
Register : DDRIOB_DIFF1 @ 0XF8000B54

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF1 @ 0XF8000B54 180 180

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

SRAM/NOR SET OPMODE

UART REGISTERS

Register : Baud_rate_divider_reg0 @ 0XE0001034

Bitfield Bits Mask Value Shifted Value

BDIV 7:0 ff 6 6

Baud_rate_divider_reg0 @ 0XE0001034 ff 6
Register : Baud_rate_gen_reg0 @ 0XE0001018

Bitfield Bits Mask Value Shifted Value

CD 15:0 ffff 3e 3e

Baud_rate_gen_reg0 @ 0XE0001018 ffff 3e
Register : Control_reg0 @ 0XE0001000

Bitfield Bits Mask Value Shifted Value

STPBRK 8:8 100 0 0

STTBRK 7:7 80 0 0

RSTTO 6:6 40 0 0

TXDIS 5:5 20 0 0

TXEN 4:4 10 1 10

RXDIS 3:3 8 0 0

RXEN 2:2 4 1 4

TXRES 1:1 2 1 2

RXRES 0:0 1 1 1

Control_reg0 @ 0XE0001000 1ff 17
Register : mode_reg0 @ 0XE0001004

Bitfield Bits Mask Value Shifted Value

IRMODE 11:11 800 0 0

UCLKEN 10:10 400 0 0

CHMODE 9:8 300 0 0

NBSTOP 7:6 c0 0 0

PAR 5:3 38 4 20

CHRL 2:1 6 0 0

CLKS 0:0 1 0 0

mode_reg0 @ 0XE0001004 fff 20

PL POWER ON RESET REGISTERS

Register : CTRL @ 0XF8007000

Bitfield Bits Mask Value Shifted Value

PCFG_POR_CNT_4K 29:29 20000000 0 0

CTRL @ 0XF8007000 20000000 0

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ps7_post_config_1_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

ENABLING LEVEL SHIFTER

Register : LVL_SHFTR_EN @ 0XF8000900

Bitfield Bits Mask Value Shifted Value

USER_INP_ICT_EN_0 1:0 3 3 3

USER_INP_ICT_EN_1 3:2 c 3 c

LVL_SHFTR_EN @ 0XF8000900 f f

FPGA RESETS TO 1

Bitfield	Bits	Mask	Value	Shifted Value
reserved_3	31:25	fe000000	7f	fe000000
FPGA_ACP_RST	24:24	1000000	1	1000000
FPGA_AXDS3_RST	23:23	800000	1	800000
FPGA_AXDS2_RST	22:22	400000	1	400000
FPGA_AXDS1_RST	21:21	200000	1	200000
FPGA_AXDS0_RST	20:20	100000	1	100000
reserved_2	19:18	c0000	3	c0000
FSSW1_FPGA_RST	17:17	20000	1	20000
FSSW0_FPGA_RST	16:16	10000	1	10000
reserved_1	15:14	c000	3	c000
FPGA_FMSW1_RST	13:13	2000	1	2000
FPGA_FMSW0_RST	12:12	1000	1	1000
FPGA_DMA3_RST	11:11	800	1	800
FPGA_DMA2_RST	10:10	400	1	400
FPGA_DMA1_RST	9:9	200	1	200
FPGA_DMA0_RST	8:8	100	1	100
reserved	7:4	f0	f	f0
FPGA3_OUT_RST	3:3	8	1	8
FPGA2_OUT_RST	2:2	4	1	4
FPGA1_OUT_RST	1:1	2	1	2
FPGA0_OUT_RST	0:0	1	1	1
FPGA_RST_CTRL @ 0XF8000240		ffffffff		ffffffff

FPGA RESETS TO 0

Bitfield	Bits	Mask	Value
reserved_3	31:25	fe000000	0
FPGA_ACP_RST	24:24	1000000	0
FPGA_AXDS3_RST	23:23	800000	0
FPGA_AXDS2_RST	22:22	400000	0
FPGA_AXDS1_RST	21:21	200000	0
FPGA_AXDS0_RST	20:20	100000	0
reserved_2	19:18	c0000	0
FSSW1_FPGA_RST	17:17	20000	0
FSSW0_FPGA_RST	16:16	10000	0
reserved_1	15:14	c000	0
FPGA_FMSW1_RST	13:13	2000	0
FPGA_FMSW0_RST	12:12	1000	0
FPGA_DMA3_RST	11:11	800	0
FPGA_DMA2_RST	10:10	400	0
FPGA_DMA1_RST	9:9	200	0
FPGA_DMA0_RST	8:8	100	0
reserved	7:4	f0	0
FPGA3_OUT_RST	3:3	8	0
FPGA2_OUT_RST	2:2	4	0
FPGA1_OUT_RST	1:1	2	0
FPGA0_OUT_RST	0:0	1	0
FPGA_RST_CTRL @ 0XF8000240		ffffffff

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

Zynq PS configuration detail

Following peripherals are selected in the design.

Peripheral Selected

Quad SPI Flash
Enet 0
USB 0
SD 0
UART 1
Timer 0
GPIO

To see detailed information please follow below links:

MIO Configuration Table
Zynq Peripheral Configuration
DDR Configuration Information
SLCR settings

PLL Init Data
Clock Init Data
DDR Init Data
MIO Init Data

MIO configuration Table

MIO Pin	Peripheral	Signal	IO type	Speed	Pullup	Direction
MIO 0	GPIO	gpio[0]	LVCMOS 3.3V	slow	disabled	inout
MIO 1	Quad SPI Flash	qspi0_ss_b	LVCMOS 3.3V	fast	disabled	out
MIO 2	Quad SPI Flash	qspi0_io[0]	LVCMOS 3.3V	fast	disabled	inout
MIO 3	Quad SPI Flash	qspi0_io[1]	LVCMOS 3.3V	fast	disabled	inout
MIO 4	Quad SPI Flash	qspi0_io[2]	LVCMOS 3.3V	fast	disabled	inout
MIO 5	Quad SPI Flash	qspi0_io[3]	LVCMOS 3.3V	fast	disabled	inout
MIO 6	Quad SPI Flash	qspi0_sclk	LVCMOS 3.3V	fast	disabled	out
MIO 7	GPIO	gpio[7]	LVCMOS 3.3V	slow	disabled	out
MIO 8	Quad SPI Flash	qspi_fbclk	LVCMOS 3.3V	fast	disabled	out
MIO 9	GPIO	gpio[9]	LVCMOS 3.3V	slow	disabled	inout
MIO 10	GPIO	gpio[10]	LVCMOS 3.3V	slow	disabled	inout
MIO 11	GPIO	gpio[11]	LVCMOS 3.3V	slow	disabled	inout
MIO 12	GPIO	gpio[12]	LVCMOS 3.3V	slow	disabled	inout
MIO 13	GPIO	gpio[13]	LVCMOS 3.3V	slow	disabled	inout
MIO 14	GPIO	gpio[14]	LVCMOS 3.3V	slow	disabled	inout
MIO 15	GPIO	gpio[15]	LVCMOS 3.3V	slow	disabled	inout
MIO 16	Enet 0	tx_clk	LVCMOS 1.8V	fast	disabled	out
MIO 17	Enet 0	txd[0]	LVCMOS 1.8V	fast	disabled	out
MIO 18	Enet 0	txd[1]	LVCMOS 1.8V	fast	disabled	out
MIO 19	Enet 0	txd[2]	LVCMOS 1.8V	fast	disabled	out
MIO 20	Enet 0	txd[3]	LVCMOS 1.8V	fast	disabled	out
MIO 21	Enet 0	tx_ctl	LVCMOS 1.8V	fast	disabled	out
MIO 22	Enet 0	rx_clk	LVCMOS 1.8V	fast	disabled	in
MIO 23	Enet 0	rxd[0]	LVCMOS 1.8V	fast	disabled	in
MIO 24	Enet 0	rxd[1]	LVCMOS 1.8V	fast	disabled	in
MIO 25	Enet 0	rxd[2]	LVCMOS 1.8V	fast	disabled	in
MIO 26	Enet 0	rxd[3]	LVCMOS 1.8V	fast	disabled	in
MIO 27	Enet 0	rx_ctl	LVCMOS 1.8V	fast	disabled	in
MIO 28	USB 0	data[4]	LVCMOS 1.8V	fast	disabled	inout
MIO 29	USB 0	dir	LVCMOS 1.8V	fast	disabled	in
MIO 30	USB 0	stp	LVCMOS 1.8V	fast	disabled	out
MIO 31	USB 0	nxt	LVCMOS 1.8V	fast	disabled	in
MIO 32	USB 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 33	USB 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 34	USB 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 35	USB 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 36	USB 0	clk	LVCMOS 1.8V	fast	disabled	in
MIO 37	USB 0	data[5]	LVCMOS 1.8V	fast	disabled	inout
MIO 38	USB 0	data[6]	LVCMOS 1.8V	fast	disabled	inout
MIO 39	USB 0	data[7]	LVCMOS 1.8V	fast	disabled	inout
MIO 40	SD 0	clk	LVCMOS 1.8V	fast	disabled	inout
MIO 41	SD 0	cmd	LVCMOS 1.8V	fast	disabled	inout
MIO 42	SD 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 43	SD 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 44	SD 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 45	SD 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 46	SD 0	wp	LVCMOS 1.8V	slow	disabled	in
MIO 47	SD 0	cd	LVCMOS 1.8V	slow	disabled	in
MIO 48	UART 1	tx	LVCMOS 1.8V	slow	disabled	out
MIO 49	UART 1	rx	LVCMOS 1.8V	slow	disabled	in
MIO 50	GPIO	gpio[50]	LVCMOS 1.8V	slow	disabled	in
MIO 51	GPIO	gpio[51]	LVCMOS 1.8V	slow	disabled	in
MIO 52	Enet 0	mdc	LVCMOS 1.8V	slow	disabled	out
MIO 53	Enet 0	mdio	LVCMOS 1.8V	slow	disabled	inout

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Zynq Peripheral Configuration

Peripheral	Signal Group	Signal	MIO
Quad SPI Flash			MIO 1 .. 6
	Dual Quad SPI (4 bit)		Disabled
	Dual Quad SPI (Parallel 8 bit)		Disabled
	Feedback Clk		MIO 8
SRAM/NOR Flash			Disabled
NAND Flash			Disabled
Enet 0			MIO 16 .. 27
		tx_clk	MIO 16
		txd[3]	MIO 20
		txd[2]	MIO 19
		txd[1]	MIO 18
		txd[0]	MIO 17
		tx_ctl	MIO 21
		rx_clk	MIO 22
		rxd[3]	MIO 26
		rxd[2]	MIO 25
		rxd[1]	MIO 24
		rxd[0]	MIO 23
		rx_ctl	MIO 27
	MDIO		MIO 52 .. 53
		mdc	MIO 52
		mdio	MIO 53
Enet 1			Disabled
USB 0			MIO 28 .. 39
		clk	MIO 36
		dir	MIO 29
		stp	MIO 30
		nxt	MIO 31
		data[0]	MIO 32
		data[1]	MIO 33
		data[2]	MIO 34
		data[3]	MIO 35
		data[4]	MIO 28
		data[5]	MIO 37
		data[6]	MIO 38
		data[7]	MIO 39
USB 1			Disabled
SD 0			MIO 40 .. 45
	CD		MIO 47
	WP		MIO 46
	Power		Disabled
SD 1			Disabled
UART 0			Disabled
UART 1			MIO 48 .. 49
		rx	MIO 49
		tx	MIO 48
	Modem Signals		Disabled
I2C 0			Disabled
I2C 1			Disabled
SPI 0			Disabled
SPI 1			Disabled
CAN 0			Disabled
CAN 1			Disabled
Trace			Disabled
Timer 0			EMIO
		clk_in	EMIO
		wave_out	EMIO
Timer 1			Disabled
Watchdog			Disabled
PJTAG			Disabled
GPIO			MIO
Mode			Disabled
VCfg			Disabled

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DDR Memory information

DDR Controller Configuration

Parameter	Value
Enable DDR	1
Memory Type	DDR 3
Memory Part	MT41J128M16 HA-15E
DRAM bus width	32 Bit
ECC	Disabled
BURST Length (lppdr only)	8
Internal Vref	1
Operating Frequency (MHz)	533.333313
HIGH temperature	Normal (0-85)

Memory Part Configuration

Parameter	Value
DRAM IC bus width	16 Bits
DRAM Device Capacity	2048 MBits
Speed Bin	DDR3_1066F
BANK Address Count	3
ROW Address Count	14
COLUMN Address Count	10
CAS Latency	7
CAS Write Latency	6
RAS to CAS Delay	7
RECHARGE Time	7
tRC (ns )	49.5
tRASmin ( ns )	36.0
tFAW	45.0
ADDITIVE Latency	0

Training/Board Details

Parameter	Value
Write levelling	1
Read gate	1
Read data eye	1
DQS to Clock delay [0] (ns)	0.025
DQS to Clock delay [1] (ns)	0.028
DQS to Clock delay [2] (ns)	-0.009
DQS to Clock delay [3] (ns)	-0.061
Board delay [0] (ns)	0.41
Board delay [1] (ns)	0.411
Board delay [2] (ns)	0.341
Board delay [3] (ns)	0.358

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ps7_pll_init_data_2_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

PLL SLCR REGISTERS

ARM PLL INIT

Register : ARM_PLL_CFG @ 0XF8000110

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 fa fa000

ARM_PLL_CFG @ 0XF8000110 3ffff0 fa220

UPDATE FB_DIV

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 28 28000

ARM_PLL_CTRL @ 0XF8000100 7f000 28000

BY PASS PLL

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

ARM_PLL_CTRL @ 0XF8000100 10 10

ASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

ARM_PLL_CTRL @ 0XF8000100 1 1

DEASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

ARM_PLL_CTRL @ 0XF8000100 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

ARM_PLL_LOCK 0:0 1 1 1

PLL_STATUS @ 0XF800010C 1 1

REMOVE PLL BY PASS

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

ARM_PLL_CTRL @ 0XF8000100 10 0

Bitfield	Bits	Mask	Value	Shifted Value
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	2	200
CPU_6OR4XCLKACT	24:24	1000000	1	1000000
CPU_3OR2XCLKACT	25:25	2000000	1	2000000
CPU_2XCLKACT	26:26	4000000	1	4000000
CPU_1XCLKACT	27:27	8000000	1	8000000
CPU_PERI_CLKACT	28:28	10000000	1	10000000
ARM_CLK_CTRL @ 0XF8000120		1f003f30		1f000200

DDR PLL INIT

Register : DDR_PLL_CFG @ 0XF8000114

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 12c 12c000

DDR_PLL_CFG @ 0XF8000114 3ffff0 12c220

UPDATE FB_DIV

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 20 20000

DDR_PLL_CTRL @ 0XF8000104 7f000 20000

BY PASS PLL

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

DDR_PLL_CTRL @ 0XF8000104 10 10

ASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

DDR_PLL_CTRL @ 0XF8000104 1 1

DEASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

DDR_PLL_CTRL @ 0XF8000104 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

DDR_PLL_LOCK 1:1 2 1 2

PLL_STATUS @ 0XF800010C 2 2

REMOVE PLL BY PASS

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

DDR_PLL_CTRL @ 0XF8000104 10 0

Register : DDR_CLK_CTRL @ 0XF8000124

Bitfield Bits Mask Value Shifted Value

DDR_3XCLKACT 0:0 1 1 1

DDR_2XCLKACT 1:1 2 1 2

DDR_3XCLK_DIVISOR 25:20 3f00000 2 200000

DDR_2XCLK_DIVISOR 31:26 fc000000 3 c000000

DDR_CLK_CTRL @ 0XF8000124 fff00003 c200003

IO PLL INIT

Register : IO_PLL_CFG @ 0XF8000118

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 c c0

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 145 145000

IO_PLL_CFG @ 0XF8000118 3ffff0 1452c0

UPDATE FB_DIV

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 1e 1e000

IO_PLL_CTRL @ 0XF8000108 7f000 1e000

BY PASS PLL

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

IO_PLL_CTRL @ 0XF8000108 10 10

ASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

IO_PLL_CTRL @ 0XF8000108 1 1

DEASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

IO_PLL_CTRL @ 0XF8000108 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

IO_PLL_LOCK 2:2 4 1 4

PLL_STATUS @ 0XF800010C 4 4

REMOVE PLL BY PASS

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

IO_PLL_CTRL @ 0XF8000108 10 0

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_clock_init_data_2_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

CLOCK CONTROL SLCR REGISTERS

Register : DCI_CLK_CTRL @ 0XF8000128

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

DIVISOR0 13:8 3f00 23 2300

DIVISOR1 25:20 3f00000 3 300000

DCI_CLK_CTRL @ 0XF8000128 3f03f01 302301
Register : GEM0_RCLK_CTRL @ 0XF8000138

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 4:4 10 0 0

GEM0_RCLK_CTRL @ 0XF8000138 11 1
Register : GEM0_CLK_CTRL @ 0XF8000140

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 6:4 70 0 0

DIVISOR 13:8 3f00 8 800

DIVISOR1 25:20 3f00000 1 100000

GEM0_CLK_CTRL @ 0XF8000140 3f03f71 100801
Register : LQSPI_CLK_CTRL @ 0XF800014C

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

LQSPI_CLK_CTRL @ 0XF800014C 3f31 501
Register : SDIO_CLK_CTRL @ 0XF8000150

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 1 1

CLKACT1 1:1 2 0 0

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

SDIO_CLK_CTRL @ 0XF8000150 3f33 1401
Register : UART_CLK_CTRL @ 0XF8000154

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 0 0

CLKACT1 1:1 2 1 2

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

UART_CLK_CTRL @ 0XF8000154 3f33 1402
Register : PCAP_CLK_CTRL @ 0XF8000168

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

PCAP_CLK_CTRL @ 0XF8000168 3f31 501
Register : FPGA0_CLK_CTRL @ 0XF8000170

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 a a00

DIVISOR1 25:20 3f00000 1 100000

FPGA0_CLK_CTRL @ 0XF8000170 3f03f30 100a00
Register : FPGA1_CLK_CTRL @ 0XF8000180

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 7 700

DIVISOR1 25:20 3f00000 1 100000

FPGA1_CLK_CTRL @ 0XF8000180 3f03f30 100700
Register : FPGA2_CLK_CTRL @ 0XF8000190

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA2_CLK_CTRL @ 0XF8000190 3f03f30 101400
Register : FPGA3_CLK_CTRL @ 0XF80001A0

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA3_CLK_CTRL @ 0XF80001A0 3f03f30 101400
Register : CLK_621_TRUE @ 0XF80001C4

Bitfield Bits Mask Value Shifted Value

CLK_621_TRUE 0:0 1 1 1

CLK_621_TRUE @ 0XF80001C4 1 1

Bitfield	Bits	Mask	Value	Shifted Value
DMA_CPU_2XCLKACT	0:0	1	1	1
USB0_CPU_1XCLKACT	2:2	4	1	4
USB1_CPU_1XCLKACT	3:3	8	1	8
GEM0_CPU_1XCLKACT	6:6	40	1	40
GEM1_CPU_1XCLKACT	7:7	80	0	0
SDI0_CPU_1XCLKACT	10:10	400	1	400
SDI1_CPU_1XCLKACT	11:11	800	0	0
SPI0_CPU_1XCLKACT	14:14	4000	0	0
SPI1_CPU_1XCLKACT	15:15	8000	0	0
CAN0_CPU_1XCLKACT	16:16	10000	0	0
CAN1_CPU_1XCLKACT	17:17	20000	0	0
I2C0_CPU_1XCLKACT	18:18	40000	1	40000
I2C1_CPU_1XCLKACT	19:19	80000	1	80000
UART0_CPU_1XCLKACT	20:20	100000	0	0
UART1_CPU_1XCLKACT	21:21	200000	1	200000
GPIO_CPU_1XCLKACT	22:22	400000	1	400000
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000
APER_CLK_CTRL @ 0XF800012C		1ffcccd		1ec044d

THIS SHOULD BE BLANK

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_ddr_init_data_2_0

DDR INITIALIZATION

LOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	0	0
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		80

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_rfc_nom_x32	11:0	fff	81	81
reg_ddrc_active_ranks	13:12	3000	1	1000
reg_ddrc_addrmap_cs_bit0	18:14	7c000	0	0
reg_ddrc_wr_odt_block	20:19	180000	1	80000
reg_ddrc_diff_rank_rd_2cycle_gap	21:21	200000	0	0
reg_ddrc_addrmap_cs_bit1	26:22	7c00000	0	0
reg_ddrc_addrmap_open_bank	27:27	8000000	0	0
reg_ddrc_addrmap_4bank_ram	28:28	10000000	0	0
Two_rank_cfg @ 0XF8006004		1fffffff		81081

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_hpr_min_non_critical_x32	10:0	7ff	f	f
reg_ddrc_hpr_max_starve_x32	21:11	3ff800	f	7800
reg_ddrc_hpr_xact_run_length	25:22	3c00000	f	3c00000
HPR_reg @ 0XF8006008		3ffffff		3c0780f

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_lpr_min_non_critical_x32	10:0	7ff	1	1
reg_ddrc_lpr_max_starve_x32	21:11	3ff800	2	1000
reg_ddrc_lpr_xact_run_length	25:22	3c00000	8	2000000
LPR_reg @ 0XF800600C		3ffffff		2001001

Register : WR_reg @ 0XF8006010

Bitfield Bits Mask Value Shifted Value

reg_ddrc_w_min_non_critical_x32 10:0 7ff 1 1

reg_ddrc_w_xact_run_length 14:11 7800 8 4000

reg_ddrc_w_max_starve_x32 25:15 3ff8000 2 10000

WR_reg @ 0XF8006010 3ffffff 14001
Register : DRAM_param_reg0 @ 0XF8006014

Bitfield Bits Mask Value Shifted Value

reg_ddrc_t_rc 5:0 3f 1b 1b

reg_ddrc_t_rfc_min 13:6 3fc0 56 1580

reg_ddrc_post_selfref_gap_x32 20:14 1fc000 10 40000

DRAM_param_reg0 @ 0XF8006014 1fffff 4159b

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_wr2pre	4:0	1f	12	12
reg_ddrc_powerdown_to_x32	9:5	3e0	6	c0
reg_ddrc_t_faw	15:10	fc00	18	6000
reg_ddrc_t_ras_max	21:16	3f0000	24	240000
reg_ddrc_t_ras_min	26:22	7c00000	14	5000000
reg_ddrc_t_cke	31:28	f0000000	4	40000000
DRAM_param_reg1 @ 0XF8006018		f7ffffff		452460d2

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_write_latency	4:0	1f	5	5
reg_ddrc_rd2wr	9:5	3e0	7	e0
reg_ddrc_wr2rd	14:10	7c00	e	3800
reg_ddrc_t_xp	19:15	f8000	4	20000
reg_ddrc_pad_pd	22:20	700000	0	0
reg_ddrc_rd2pre	27:23	f800000	4	2000000
reg_ddrc_t_rcd	31:28	f0000000	7	70000000
DRAM_param_reg2 @ 0XF800601C		ffffffff		720238e5

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_ccd	4:2	1c	4	10
reg_ddrc_t_rrd	7:5	e0	6	c0
reg_ddrc_refresh_margin	11:8	f00	2	200
reg_ddrc_t_rp	15:12	f000	7	7000
reg_ddrc_refresh_to_x32	20:16	1f0000	8	80000
reg_ddrc_sdram	21:21	200000	1	200000
reg_ddrc_mobile	22:22	400000	0	0
reg_ddrc_clock_stop_en	23:23	800000	0	0
reg_ddrc_read_latency	28:24	1f000000	7	7000000
reg_phy_mode_ddr1_ddr2	29:29	20000000	1	20000000
reg_ddrc_dis_pad_pd	30:30	40000000	0	0
reg_ddrc_loopback	31:31	80000000	0	0
DRAM_param_reg3 @ 0XF8006020		fffffffc		272872d0

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_en_2t_timing_mode	0:0	1	0	0
reg_ddrc_prefer_write	1:1	2	0	0
reg_ddrc_max_rank_rd	5:2	3c	f	3c
reg_ddrc_mr_wr	6:6	40	0	0
reg_ddrc_mr_addr	8:7	180	0	0
reg_ddrc_mr_data	24:9	1fffe00	0	0
ddrc_reg_mr_wr_busy	25:25	2000000	0	0
reg_ddrc_mr_type	26:26	4000000	0	0
reg_ddrc_mr_rdata_valid	27:27	8000000	0	0
DRAM_param_reg4 @ 0XF8006024		fffffff		3c

Register : DRAM_init_param @ 0XF8006028

Bitfield Bits Mask Value Shifted Value

reg_ddrc_final_wait_x32 6:0 7f 7 7

reg_ddrc_pre_ocd_x32 10:7 780 0 0

reg_ddrc_t_mrd 13:11 3800 4 2000

DRAM_init_param @ 0XF8006028 3fff 2007
Register : DRAM_EMR_reg @ 0XF800602C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_emr2 15:0 ffff 8 8

reg_ddrc_emr3 31:16 ffff0000 0 0

DRAM_EMR_reg @ 0XF800602C ffffffff 8
Register : DRAM_EMR_MR_reg @ 0XF8006030

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr 15:0 ffff 930 930

reg_ddrc_emr 31:16 ffff0000 4 40000

DRAM_EMR_MR_reg @ 0XF8006030 ffffffff 40930

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_burst_rdwr	3:0	f	4	4
reg_ddrc_pre_cke_x1024	13:4	3ff0	69	690
reg_ddrc_post_cke_x1024	25:16	3ff0000	1	10000
reg_ddrc_burstchop	28:28	10000000	0	0
DRAM_burst8_rdwr @ 0XF8006034		13ff3fff		10694

Bitfield	Bits	Mask	Value
reg_ddrc_force_low_pri_n	0:0	1	0
reg_ddrc_dis_dq	1:1	2	0
reg_phy_debug_mode	6:6	40	0
reg_phy_wr_level_start	7:7	80	0
reg_phy_rd_level_start	8:8	100	0
reg_phy_dq0_wait_t	12:9	1e00	0
DRAM_disable_DQ @ 0XF8006038		1fc3

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_bank_b0	3:0	f	7	7
reg_ddrc_addrmap_bank_b1	7:4	f0	7	70
reg_ddrc_addrmap_bank_b2	11:8	f00	7	700
reg_ddrc_addrmap_col_b5	15:12	f000	0	0
reg_ddrc_addrmap_col_b6	19:16	f0000	0	0
DRAM_addr_map_bank @ 0XF800603C		fffff		777

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_col_b2	3:0	f	0	0
reg_ddrc_addrmap_col_b3	7:4	f0	0	0
reg_ddrc_addrmap_col_b4	11:8	f00	0	0
reg_ddrc_addrmap_col_b7	15:12	f000	0	0
reg_ddrc_addrmap_col_b8	19:16	f0000	0	0
reg_ddrc_addrmap_col_b9	23:20	f00000	f	f00000
reg_ddrc_addrmap_col_b10	27:24	f000000	f	f000000
reg_ddrc_addrmap_col_b11	31:28	f0000000	f	f0000000
DRAM_addr_map_col @ 0XF8006040		ffffffff		fff00000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_row_b0	3:0	f	6	6
reg_ddrc_addrmap_row_b1	7:4	f0	6	60
reg_ddrc_addrmap_row_b2_11	11:8	f00	6	600
reg_ddrc_addrmap_row_b12	15:12	f000	6	6000
reg_ddrc_addrmap_row_b13	19:16	f0000	6	60000
reg_ddrc_addrmap_row_b14	23:20	f00000	f	f00000
reg_ddrc_addrmap_row_b15	27:24	f000000	f	f000000
DRAM_addr_map_row @ 0XF8006044		fffffff		ff66666

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_rank0_rd_odt	2:0	7	0	0
reg_ddrc_rank0_wr_odt	5:3	38	1	8
reg_ddrc_rank1_rd_odt	8:6	1c0	1	40
reg_ddrc_rank1_wr_odt	11:9	e00	1	200
reg_phy_rd_local_odt	13:12	3000	0	0
reg_phy_wr_local_odt	15:14	c000	3	c000
reg_phy_idle_local_odt	17:16	30000	3	30000
reg_ddrc_rank2_rd_odt	20:18	1c0000	0	0
reg_ddrc_rank2_wr_odt	23:21	e00000	0	0
reg_ddrc_rank3_rd_odt	26:24	7000000	0	0
reg_ddrc_rank3_wr_odt	29:27	38000000	0	0
DRAM_ODT_reg @ 0XF8006048		3fffffff		3c248

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_rd_cmd_to_data	3:0	f	0	0
reg_phy_wr_cmd_to_data	7:4	f0	0	0
reg_phy_rdc_we_to_re_delay	11:8	f00	8	800
reg_phy_rdc_fifo_rst_disable	15:15	8000	0	0
reg_phy_use_fixed_re	16:16	10000	1	10000
reg_phy_rdc_fifo_rst_err_cnt_clr	17:17	20000	0	0
reg_phy_dis_phy_ctrl_rstn	18:18	40000	0	0
reg_phy_clk_stall_level	19:19	80000	0	0
reg_phy_gatelvl_num_of_dq0	27:24	f000000	7	7000000
reg_phy_wrlvl_num_of_dq0	31:28	f0000000	7	70000000
phy_cmd_timeout_rddata_cpt @ 0XF8006050		ff0f8fff		77010800

Register : DLL_calib @ 0XF8006058

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dll_calib_to_min_x1024 7:0 ff 1 1

reg_ddrc_dll_calib_to_max_x1024 15:8 ff00 1 100

reg_ddrc_dis_dll_calib 16:16 10000 0 0

DLL_calib @ 0XF8006058 1ffff 101
Register : ODT_delay_hold @ 0XF800605C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_rd_odt_delay 3:0 f 3 3

reg_ddrc_wr_odt_delay 7:4 f0 0 0

reg_ddrc_rd_odt_hold 11:8 f00 0 0

reg_ddrc_wr_odt_hold 15:12 f000 5 5000

ODT_delay_hold @ 0XF800605C ffff 5003

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_pageclose	0:0	1	0	0
reg_ddrc_lpr_num_entries	6:1	7e	1f	3e
reg_ddrc_auto_pre_en	7:7	80	0	0
reg_ddrc_refresh_update_level	8:8	100	0	0
reg_ddrc_dis_wc	9:9	200	0	0
reg_ddrc_dis_collision_page_opt	10:10	400	0	0
reg_ddrc_selfref_en	12:12	1000	0	0
ctrl_reg1 @ 0XF8006060		17ff		3e

Register : ctrl_reg2 @ 0XF8006064

Bitfield Bits Mask Value Shifted Value

reg_ddrc_go2critical_hysteresis 12:5 1fe0 0 0

reg_arb_go2critical_en 17:17 20000 1 20000

ctrl_reg2 @ 0XF8006064 21fe0 20000
Register : ctrl_reg3 @ 0XF8006068

Bitfield Bits Mask Value Shifted Value

reg_ddrc_wrlvl_ww 7:0 ff 41 41

reg_ddrc_rdlvl_rr 15:8 ff00 41 4100

reg_ddrc_dfi_t_wlmrd 25:16 3ff0000 28 280000

ctrl_reg3 @ 0XF8006068 3ffffff 284141
Register : ctrl_reg4 @ 0XF800606C

Bitfield Bits Mask Value Shifted Value

dfi_t_ctrlupd_interval_min_x1024 7:0 ff 10 10

dfi_t_ctrlupd_interval_max_x1024 15:8 ff00 16 1600

ctrl_reg4 @ 0XF800606C ffff 1610

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dfi_t_ctrl_delay	3:0	f	1	1
reg_ddrc_dfi_t_dram_clk_disable	7:4	f0	1	10
reg_ddrc_dfi_t_dram_clk_enable	11:8	f00	1	100
reg_ddrc_t_cksre	15:12	f000	6	6000
reg_ddrc_t_cksrx	19:16	f0000	6	60000
reg_ddrc_t_ckesr	25:20	3f00000	4	400000
ctrl_reg5 @ 0XF8006078		3ffffff		466111

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_ckpde	3:0	f	2	2
reg_ddrc_t_ckpdx	7:4	f0	2	20
reg_ddrc_t_ckdpde	11:8	f00	2	200
reg_ddrc_t_ckdpdx	15:12	f000	2	2000
reg_ddrc_t_ckcsx	19:16	f0000	3	30000
ctrl_reg6 @ 0XF800607C		fffff		32222

Register : CHE_REFRESH_TIMER01 @ 0XF80060A0

Bitfield Bits Mask Value Shifted Value

refresh_timer0_start_value_x32 11:0 fff 0 0

refresh_timer1_start_value_x32 23:12 fff000 8 8000

CHE_REFRESH_TIMER01 @ 0XF80060A0 ffffff 8000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dis_auto_zq	0:0	1	0	0
reg_ddrc_ddr3	1:1	2	1	2
reg_ddrc_t_mod	11:2	ffc	200	800
reg_ddrc_t_zq_long_nop	21:12	3ff000	200	200000
reg_ddrc_t_zq_short_nop	31:22	ffc00000	40	10000000
CHE_T_ZQ @ 0XF80060A4		ffffffff		10200802

Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8

Bitfield Bits Mask Value Shifted Value

t_zq_short_interval_x1024 19:0 fffff cb73 cb73

dram_rstn_x1024 27:20 ff00000 69 6900000

CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8 fffffff 690cb73
Register : deep_pwrdwn_reg @ 0XF80060AC

Bitfield Bits Mask Value Shifted Value

deeppowerdown_en 0:0 1 0 0

deeppowerdown_to_x1024 8:1 1fe ff 1fe

deep_pwrdwn_reg @ 0XF80060AC 1ff 1fe

Bitfield	Bits	Mask	Value	Shifted Value
dfi_wrlvl_max_x1024	11:0	fff	fff	fff
dfi_rdlvl_max_x1024	23:12	fff000	fff	fff000
ddrc_reg_twrlvl_max_error	24:24	1000000	0	0
ddrc_reg_trdlvl_max_error	25:25	2000000	0	0
reg_ddrc_dfi_wr_level_en	26:26	4000000	1	4000000
reg_ddrc_dfi_rd_dqs_gate_level	27:27	8000000	1	8000000
reg_ddrc_dfi_rd_data_eye_train	28:28	10000000	1	10000000
reg_2c @ 0XF80060B0		1fffffff		1cffffff

Register : reg_2d @ 0XF80060B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_2t_delay 8:0 1ff 0 0

reg_ddrc_skip_ocd 9:9 200 1 200

reg_ddrc_dis_pre_bypass 10:10 400 0 0

reg_2d @ 0XF80060B4 7ff 200
Register : dfi_timing @ 0XF80060B8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dfi_t_rddata_en 4:0 1f 6 6

reg_ddrc_dfi_t_ctrlup_min 14:5 7fe0 3 60

reg_ddrc_dfi_t_ctrlup_max 24:15 1ff8000 40 200000

dfi_timing @ 0XF80060B8 1ffffff 200066
Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4

Bitfield Bits Mask Value Shifted Value

Clear_Uncorrectable_DRAM_ECC_error 0:0 1 0 0

Clear_Correctable_DRAM_ECC_error 1:1 2 0 0

CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4 3 0
Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8

Bitfield Bits Mask Value Shifted Value

CORR_ECC_LOG_VALID 0:0 1 0 0

ECC_CORRECTED_BIT_NUM 7:1 fe 0 0

CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8 ff 0
Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC

Bitfield Bits Mask Value Shifted Value

UNCORR_ECC_LOG_VALID 0:0 1 0 0

CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC 1 0
Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0

Bitfield Bits Mask Value Shifted Value

STAT_NUM_CORR_ERR 15:8 ff00 0 0

STAT_NUM_UNCORR_ERR 7:0 ff 0 0

CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0 ffff 0
Register : ECC_scrub @ 0XF80060F4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_ecc_mode 2:0 7 0 0

reg_ddrc_dis_scrub 3:3 8 1 8

ECC_scrub @ 0XF80060F4 f 8
Register : phy_rcvr_enable @ 0XF8006114

Bitfield Bits Mask Value Shifted Value

reg_phy_dif_on 3:0 f 0 0

reg_phy_dif_off 7:4 f0 0 0

phy_rcvr_enable @ 0XF8006114 ff 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config0 @ 0XF8006118		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config1 @ 0XF800611C		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config2 @ 0XF8006120		7fffffff		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_board_lpbk_tx	4:4	10	0	0
reg_phy_board_lpbk_rx	5:5	20	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config3 @ 0XF8006124		7fffffff		40000001

Register : phy_init_ratio0 @ 0XF800612C

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 cf 33c00

phy_init_ratio0 @ 0XF800612C fffff 33c03
Register : phy_init_ratio1 @ 0XF8006130

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 d0 34000

phy_init_ratio1 @ 0XF8006130 fffff 34003
Register : phy_init_ratio2 @ 0XF8006134

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 bd 2f400

phy_init_ratio2 @ 0XF8006134 fffff 2f400
Register : phy_init_ratio3 @ 0XF8006138

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 c1 30400

phy_init_ratio3 @ 0XF8006138 fffff 30400
Register : phy_rd_dqs_cfg0 @ 0XF8006140

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg0 @ 0XF8006140 fffff 35
Register : phy_rd_dqs_cfg1 @ 0XF8006144

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg1 @ 0XF8006144 fffff 35
Register : phy_rd_dqs_cfg2 @ 0XF8006148

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg2 @ 0XF8006148 fffff 35
Register : phy_rd_dqs_cfg3 @ 0XF800614C

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg3 @ 0XF800614C fffff 35
Register : phy_wr_dqs_cfg0 @ 0XF8006154

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg0 @ 0XF8006154 fffff 83
Register : phy_wr_dqs_cfg1 @ 0XF8006158

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg1 @ 0XF8006158 fffff 83
Register : phy_wr_dqs_cfg2 @ 0XF800615C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 7f 7f

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg2 @ 0XF800615C fffff 7f
Register : phy_wr_dqs_cfg3 @ 0XF8006160

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 78 78

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg3 @ 0XF8006160 fffff 78
Register : phy_we_cfg0 @ 0XF8006168

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 124 124

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg0 @ 0XF8006168 1fffff 124
Register : phy_we_cfg1 @ 0XF800616C

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 125 125

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg1 @ 0XF800616C 1fffff 125
Register : phy_we_cfg2 @ 0XF8006170

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 112 112

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg2 @ 0XF8006170 1fffff 112
Register : phy_we_cfg3 @ 0XF8006174

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 116 116

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg3 @ 0XF8006174 1fffff 116
Register : wr_data_slv0 @ 0XF800617C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv0 @ 0XF800617C fffff c3
Register : wr_data_slv1 @ 0XF8006180

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv1 @ 0XF8006180 fffff c3
Register : wr_data_slv2 @ 0XF8006184

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff bf bf

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv2 @ 0XF8006184 fffff bf
Register : wr_data_slv3 @ 0XF8006188

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff b8 b8

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv3 @ 0XF8006188 fffff b8

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_loopback	0:0	1	0	0
reg_phy_bl2	1:1	2	0	0
reg_phy_at_spd_atpg	2:2	4	0	0
reg_phy_bist_enable	3:3	8	0	0
reg_phy_bist_force_err	4:4	10	0	0
reg_phy_bist_mode	6:5	60	0	0
reg_phy_invert_clkout	7:7	80	1	80
reg_phy_all_dq_mpr_rd_resp	8:8	100	0	0
reg_phy_sel_logic	9:9	200	0	0
reg_phy_ctrl_slave_ratio	19:10	ffc00	100	40000
reg_phy_ctrl_slave_force	20:20	100000	0	0
reg_phy_ctrl_slave_delay	27:21	fe00000	0	0
reg_phy_use_rank0_delays	28:28	10000000	1	10000000
reg_phy_lpddr	29:29	20000000	0	0
reg_phy_cmd_latency	30:30	40000000	0	0
reg_phy_int_lpbk	31:31	80000000	0	0
reg_64 @ 0XF8006190		ffffffff		10040080

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wr_rl_delay	4:0	1f	2	2
reg_phy_rd_rl_delay	9:5	3e0	4	80
reg_phy_dll_lock_diff	13:10	3c00	f	3c00
reg_phy_use_wr_level	14:14	4000	1	4000
reg_phy_use_rd_dqs_gate_level	15:15	8000	1	8000
reg_phy_use_rd_data_eye_level	16:16	10000	1	10000
reg_phy_dis_calib_rst	17:17	20000	0	0
reg_phy_ctrl_slave_delay	19:18	c0000	0	0
reg_65 @ 0XF8006194		fffff		1fc82

Register : page_mask @ 0XF8006204

Bitfield Bits Mask Value Shifted Value

reg_arb_page_addr_mask 31:0 0 0 0

page_mask @ 0XF8006204 0 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port0 @ 0XF8006208		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port1 @ 0XF800620C		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port2 @ 0XF8006210		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
reg_arb_dis_rmw_portn	19:19	80000	1	80000
axi_priority_wr_port3 @ 0XF8006214		f03ff		803ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port0 @ 0XF8006218		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port1 @ 0XF800621C		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port2 @ 0XF8006220		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port3 @ 0XF8006224		f03ff		3ff

Register : lpddr_ctrl0 @ 0XF80062A8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_lpddr2 0:0 1 0 0

reg_ddrc_per_bank_refresh 1:1 2 0 0

reg_ddrc_derate_enable 2:2 4 0 0

reg_ddrc_mr4_margin 11:4 ff0 0 0

lpddr_ctrl0 @ 0XF80062A8 ff7 0
Register : lpddr_ctrl1 @ 0XF80062AC

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr4_read_interval 31:0 0 0 0

lpddr_ctrl1 @ 0XF80062AC 0 0
Register : lpddr_ctrl2 @ 0XF80062B0

Bitfield Bits Mask Value Shifted Value

reg_ddrc_min_stable_clock_x1 3:0 f 5 5

reg_ddrc_idle_after_reset_x32 11:4 ff0 12 120

reg_ddrc_t_mrw 21:12 3ff000 5 5000

lpddr_ctrl2 @ 0XF80062B0 3fffff 5125
Register : lpddr_ctrl3 @ 0XF80062B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_max_auto_init_x1024 7:0 ff a8 a8

reg_ddrc_dev_zqinit_x32 17:8 3ff00 12 1200

lpddr_ctrl3 @ 0XF80062B4 3ffff 12a8

POLL ON DCI STATUS

Register : DDRIOB_DCI_STATUS @ 0XF8000B74

Bitfield Bits Mask Value Shifted Value

DONE 13:13 2000 1 2000

DDRIOB_DCI_STATUS @ 0XF8000B74 2000 2000

UNLOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	1	1
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		81

CHECK DDR STATUS

Register : mode_sts_reg @ 0XF8006054

Bitfield Bits Mask Value Shifted Value

ddrc_reg_operating_mode 2:0 7 1 1

mode_sts_reg @ 0XF8006054 7 1

ps7_mio_init_data_2_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

OCM REMAPPING

DDRIOB SETTINGS

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR0 @ 0XF8000B40		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR1 @ 0XF8000B44		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	1	2
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA0 @ 0XF8000B48		fff		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	1	2
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA1 @ 0XF8000B4C		fff		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	2	4
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF0 @ 0XF8000B50		fff		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	2	4
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCR_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF1 @ 0XF8000B54		fff		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_POWER	0:0	1	0	0
INP_TYPE	2:1	6	0	0
DCI_UPDATE	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCR_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_CLOCK @ 0XF8000B58		fff		600

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	1a	68000
SLEW_N	23:19	f80000	1a	d00000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C		ffffffff		d6861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	6	18000
SLEW_N	23:19	f80000	1f	f80000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60		ffffffff		f9861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	6	18000
SLEW_N	23:19	f80000	1f	f80000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64		ffffffff		f9861c

Bitfield	Bits	Mask	Value	Shifted Value
DRIVE_P	6:0	7f	1c	1c
DRIVE_N	13:7	3f80	c	600
SLEW_P	18:14	7c000	1a	68000
SLEW_N	23:19	f80000	1a	d00000
GTL	26:24	7000000	0	0
RTERM	31:27	f8000000	0	0
DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68		ffffffff		d6861c

Bitfield	Bits	Mask	Value	Shifted Value
VREF_INT_EN	0:0	1	1	1
VREF_SEL	4:1	1e	4	8
VREF_EXT_EN	6:5	60	0	0
VREF_PULLUP_EN	8:7	180	0	0
REFIO_EN	9:9	200	1	200
REFIO_TEST	11:10	c00	3	c00
REFIO_PULLUP_EN	12:12	1000	0	0
DRST_B_PULLUP_EN	13:13	2000	0	0
CKE_PULLUP_EN	14:14	4000	0	0
DDRIOB_DDR_CTRL @ 0XF8000B6C		7fff		e09

ASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 1 1

VRN_OUT 5:5 20 1 20

DDRIOB_DCI_CTRL @ 0XF8000B70 21 21

DEASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 0 0

VRN_OUT 5:5 20 1 20

DDRIOB_DCI_CTRL @ 0XF8000B70 21 20

Bitfield	Bits	Mask	Value	Shifted Value
RESET	0:0	1	1	1
ENABLE	1:1	2	1	2
VRP_TRI	2:2	4	0	0
VRN_TRI	3:3	8	0	0
VRP_OUT	4:4	10	0	0
VRN_OUT	5:5	20	1	20
NREF_OPT1	7:6	c0	0	0
NREF_OPT2	10:8	700	0	0
NREF_OPT4	13:11	3800	1	800
PREF_OPT1	16:14	1c000	0	0
PREF_OPT2	19:17	e0000	0	0
UPDATE_CONTROL	20:20	100000	0	0
INIT_COMPLETE	21:21	200000	0	0
TST_CLK	22:22	400000	0	0
TST_HLN	23:23	800000	0	0
TST_HLP	24:24	1000000	0	0
TST_RST	25:25	2000000	0	0
INT_DCI_EN	26:26	4000000	0	0
DDRIOB_DCI_CTRL @ 0XF8000B70		7ffffff		823

MIO PROGRAMMING

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_00 @ 0XF8000700		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_01 @ 0XF8000704		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_02 @ 0XF8000708		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_03 @ 0XF800070C		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_04 @ 0XF8000710		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_05 @ 0XF8000714		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_06 @ 0XF8000718		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_07 @ 0XF800071C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_08 @ 0XF8000720		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_09 @ 0XF8000724		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_10 @ 0XF8000728		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_11 @ 0XF800072C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_12 @ 0XF8000730		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_13 @ 0XF8000734		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_14 @ 0XF8000738		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_15 @ 0XF800073C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_16 @ 0XF8000740		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_17 @ 0XF8000744		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_18 @ 0XF8000748		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_19 @ 0XF800074C		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_20 @ 0XF8000750		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_21 @ 0XF8000754		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_22 @ 0XF8000758		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_23 @ 0XF800075C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_24 @ 0XF8000760		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_25 @ 0XF8000764		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_26 @ 0XF8000768		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_27 @ 0XF800076C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_28 @ 0XF8000770		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_29 @ 0XF8000774		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_30 @ 0XF8000778		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_31 @ 0XF800077C		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_32 @ 0XF8000780		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_33 @ 0XF8000784		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_34 @ 0XF8000788		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_35 @ 0XF800078C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_36 @ 0XF8000790		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_37 @ 0XF8000794		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_38 @ 0XF8000798		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_39 @ 0XF800079C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_40 @ 0XF80007A0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_41 @ 0XF80007A4		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_42 @ 0XF80007A8		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_43 @ 0XF80007AC		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_44 @ 0XF80007B0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_45 @ 0XF80007B4		3fff		380

Register : MIO_PIN_46 @ 0XF80007B8

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_46 @ 0XF80007B8 3f01 201
Register : MIO_PIN_47 @ 0XF80007BC

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_47 @ 0XF80007BC 3f01 201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_48 @ 0XF80007C0		3fff		2e0

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_49 @ 0XF80007C4		3fff		2e1

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_50 @ 0XF80007C8		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_51 @ 0XF80007CC		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_52 @ 0XF80007D0		3fff		280

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_53 @ 0XF80007D4		3fff		280

Register : SD0_WP_CD_SEL @ 0XF8000830

Bitfield Bits Mask Value Shifted Value

SDIO0_WP_SEL 5:0 3f 2e 2e

SDIO0_CD_SEL 21:16 3f0000 2f 2f0000

SD0_WP_CD_SEL @ 0XF8000830 3f003f 2f002e

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_peripherals_init_data_2_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register : DDRIOB_DATA0 @ 0XF8000B48

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA0 @ 0XF8000B48 180 180
Register : DDRIOB_DATA1 @ 0XF8000B4C

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA1 @ 0XF8000B4C 180 180
Register : DDRIOB_DIFF0 @ 0XF8000B50

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF0 @ 0XF8000B50 180 180
Register : DDRIOB_DIFF1 @ 0XF8000B54

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF1 @ 0XF8000B54 180 180

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

SRAM/NOR SET OPMODE

UART REGISTERS

Register : Baud_rate_divider_reg0 @ 0XE0001034

Bitfield Bits Mask Value Shifted Value

BDIV 7:0 ff 6 6

Baud_rate_divider_reg0 @ 0XE0001034 ff 6
Register : Baud_rate_gen_reg0 @ 0XE0001018

Bitfield Bits Mask Value Shifted Value

CD 15:0 ffff 3e 3e

Baud_rate_gen_reg0 @ 0XE0001018 ffff 3e
Register : Control_reg0 @ 0XE0001000

Bitfield Bits Mask Value Shifted Value

STPBRK 8:8 100 0 0

STTBRK 7:7 80 0 0

RSTTO 6:6 40 0 0

TXDIS 5:5 20 0 0

TXEN 4:4 10 1 10

RXDIS 3:3 8 0 0

RXEN 2:2 4 1 4

TXRES 1:1 2 1 2

RXRES 0:0 1 1 1

Control_reg0 @ 0XE0001000 1ff 17
Register : mode_reg0 @ 0XE0001004

Bitfield Bits Mask Value Shifted Value

IRMODE 11:11 800 0 0

UCLKEN 10:10 400 0 0

CHMODE 9:8 300 0 0

NBSTOP 7:6 c0 0 0

PAR 5:3 38 4 20

CHRL 2:1 6 0 0

CLKS 0:0 1 0 0

mode_reg0 @ 0XE0001004 fff 20

QSPI REGISTERS

Register : Config_reg @ 0XE000D000

Bitfield Bits Mask Value Shifted Value

Holdb_dr 19:19 80000 1 80000

Config_reg @ 0XE000D000 80000 80000

PL POWER ON RESET REGISTERS

Register : CTRL @ 0XF8007000

Bitfield Bits Mask Value Shifted Value

PCFG_POR_CNT_4K 29:29 20000000 0 0

CTRL @ 0XF8007000 20000000 0

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ps7_post_config_2_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

ENABLING LEVEL SHIFTER

Register : LVL_SHFTR_EN @ 0XF8000900

Bitfield Bits Mask Value Shifted Value

USER_INP_ICT_EN_0 1:0 3 3 3

USER_INP_ICT_EN_1 3:2 c 3 c

LVL_SHFTR_EN @ 0XF8000900 f f

FPGA RESETS TO 1

Bitfield	Bits	Mask	Value	Shifted Value
reserved_3	31:25	fe000000	7f	fe000000
FPGA_ACP_RST	24:24	1000000	1	1000000
FPGA_AXDS3_RST	23:23	800000	1	800000
FPGA_AXDS2_RST	22:22	400000	1	400000
FPGA_AXDS1_RST	21:21	200000	1	200000
FPGA_AXDS0_RST	20:20	100000	1	100000
reserved_2	19:18	c0000	3	c0000
FSSW1_FPGA_RST	17:17	20000	1	20000
FSSW0_FPGA_RST	16:16	10000	1	10000
reserved_1	15:14	c000	3	c000
FPGA_FMSW1_RST	13:13	2000	1	2000
FPGA_FMSW0_RST	12:12	1000	1	1000
FPGA_DMA3_RST	11:11	800	1	800
FPGA_DMA2_RST	10:10	400	1	400
FPGA_DMA1_RST	9:9	200	1	200
FPGA_DMA0_RST	8:8	100	1	100
reserved	7:4	f0	f	f0
FPGA3_OUT_RST	3:3	8	1	8
FPGA2_OUT_RST	2:2	4	1	4
FPGA1_OUT_RST	1:1	2	1	2
FPGA0_OUT_RST	0:0	1	1	1
FPGA_RST_CTRL @ 0XF8000240		ffffffff		ffffffff

FPGA RESETS TO 0

Bitfield	Bits	Mask	Value
reserved_3	31:25	fe000000	0
FPGA_ACP_RST	24:24	1000000	0
FPGA_AXDS3_RST	23:23	800000	0
FPGA_AXDS2_RST	22:22	400000	0
FPGA_AXDS1_RST	21:21	200000	0
FPGA_AXDS0_RST	20:20	100000	0
reserved_2	19:18	c0000	0
FSSW1_FPGA_RST	17:17	20000	0
FSSW0_FPGA_RST	16:16	10000	0
reserved_1	15:14	c000	0
FPGA_FMSW1_RST	13:13	2000	0
FPGA_FMSW0_RST	12:12	1000	0
FPGA_DMA3_RST	11:11	800	0
FPGA_DMA2_RST	10:10	400	0
FPGA_DMA1_RST	9:9	200	0
FPGA_DMA0_RST	8:8	100	0
reserved	7:4	f0	0
FPGA3_OUT_RST	3:3	8	0
FPGA2_OUT_RST	2:2	4	0
FPGA1_OUT_RST	1:1	2	0
FPGA0_OUT_RST	0:0	1	0
FPGA_RST_CTRL @ 0XF8000240		ffffffff

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

Zynq PS configuration detail

Following peripherals are selected in the design.

Peripheral Selected

Quad SPI Flash
Enet 0
USB 0
SD 0
UART 1
Timer 0
GPIO

To see detailed information please follow below links:

MIO Configuration Table
Zynq Peripheral Configuration
DDR Configuration Information
SLCR settings

PLL Init Data
Clock Init Data
DDR Init Data
MIO Init Data

MIO configuration Table

MIO Pin	Peripheral	Signal	IO type	Speed	Pullup	Direction
MIO 0	GPIO	gpio[0]	LVCMOS 3.3V	slow	disabled	inout
MIO 1	Quad SPI Flash	qspi0_ss_b	LVCMOS 3.3V	fast	disabled	out
MIO 2	Quad SPI Flash	qspi0_io[0]	LVCMOS 3.3V	fast	disabled	inout
MIO 3	Quad SPI Flash	qspi0_io[1]	LVCMOS 3.3V	fast	disabled	inout
MIO 4	Quad SPI Flash	qspi0_io[2]	LVCMOS 3.3V	fast	disabled	inout
MIO 5	Quad SPI Flash	qspi0_io[3]	LVCMOS 3.3V	fast	disabled	inout
MIO 6	Quad SPI Flash	qspi0_sclk	LVCMOS 3.3V	fast	disabled	out
MIO 7	GPIO	gpio[7]	LVCMOS 3.3V	slow	disabled	out
MIO 8	Quad SPI Flash	qspi_fbclk	LVCMOS 3.3V	fast	disabled	out
MIO 9	GPIO	gpio[9]	LVCMOS 3.3V	slow	disabled	inout
MIO 10	GPIO	gpio[10]	LVCMOS 3.3V	slow	disabled	inout
MIO 11	GPIO	gpio[11]	LVCMOS 3.3V	slow	disabled	inout
MIO 12	GPIO	gpio[12]	LVCMOS 3.3V	slow	disabled	inout
MIO 13	GPIO	gpio[13]	LVCMOS 3.3V	slow	disabled	inout
MIO 14	GPIO	gpio[14]	LVCMOS 3.3V	slow	disabled	inout
MIO 15	GPIO	gpio[15]	LVCMOS 3.3V	slow	disabled	inout
MIO 16	Enet 0	tx_clk	LVCMOS 1.8V	fast	disabled	out
MIO 17	Enet 0	txd[0]	LVCMOS 1.8V	fast	disabled	out
MIO 18	Enet 0	txd[1]	LVCMOS 1.8V	fast	disabled	out
MIO 19	Enet 0	txd[2]	LVCMOS 1.8V	fast	disabled	out
MIO 20	Enet 0	txd[3]	LVCMOS 1.8V	fast	disabled	out
MIO 21	Enet 0	tx_ctl	LVCMOS 1.8V	fast	disabled	out
MIO 22	Enet 0	rx_clk	LVCMOS 1.8V	fast	disabled	in
MIO 23	Enet 0	rxd[0]	LVCMOS 1.8V	fast	disabled	in
MIO 24	Enet 0	rxd[1]	LVCMOS 1.8V	fast	disabled	in
MIO 25	Enet 0	rxd[2]	LVCMOS 1.8V	fast	disabled	in
MIO 26	Enet 0	rxd[3]	LVCMOS 1.8V	fast	disabled	in
MIO 27	Enet 0	rx_ctl	LVCMOS 1.8V	fast	disabled	in
MIO 28	USB 0	data[4]	LVCMOS 1.8V	fast	disabled	inout
MIO 29	USB 0	dir	LVCMOS 1.8V	fast	disabled	in
MIO 30	USB 0	stp	LVCMOS 1.8V	fast	disabled	out
MIO 31	USB 0	nxt	LVCMOS 1.8V	fast	disabled	in
MIO 32	USB 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 33	USB 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 34	USB 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 35	USB 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 36	USB 0	clk	LVCMOS 1.8V	fast	disabled	in
MIO 37	USB 0	data[5]	LVCMOS 1.8V	fast	disabled	inout
MIO 38	USB 0	data[6]	LVCMOS 1.8V	fast	disabled	inout
MIO 39	USB 0	data[7]	LVCMOS 1.8V	fast	disabled	inout
MIO 40	SD 0	clk	LVCMOS 1.8V	fast	disabled	inout
MIO 41	SD 0	cmd	LVCMOS 1.8V	fast	disabled	inout
MIO 42	SD 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 43	SD 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 44	SD 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 45	SD 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 46	SD 0	wp	LVCMOS 1.8V	slow	disabled	in
MIO 47	SD 0	cd	LVCMOS 1.8V	slow	disabled	in
MIO 48	UART 1	tx	LVCMOS 1.8V	slow	disabled	out
MIO 49	UART 1	rx	LVCMOS 1.8V	slow	disabled	in
MIO 50	GPIO	gpio[50]	LVCMOS 1.8V	slow	disabled	in
MIO 51	GPIO	gpio[51]	LVCMOS 1.8V	slow	disabled	in
MIO 52	Enet 0	mdc	LVCMOS 1.8V	slow	disabled	out
MIO 53	Enet 0	mdio	LVCMOS 1.8V	slow	disabled	inout

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Zynq Peripheral Configuration

Peripheral	Signal Group	Signal	MIO
Quad SPI Flash			MIO 1 .. 6
	Dual Quad SPI (4 bit)		Disabled
	Dual Quad SPI (Parallel 8 bit)		Disabled
	Feedback Clk		MIO 8
SRAM/NOR Flash			Disabled
NAND Flash			Disabled
Enet 0			MIO 16 .. 27
		tx_clk	MIO 16
		txd[3]	MIO 20
		txd[2]	MIO 19
		txd[1]	MIO 18
		txd[0]	MIO 17
		tx_ctl	MIO 21
		rx_clk	MIO 22
		rxd[3]	MIO 26
		rxd[2]	MIO 25
		rxd[1]	MIO 24
		rxd[0]	MIO 23
		rx_ctl	MIO 27
	MDIO		MIO 52 .. 53
		mdc	MIO 52
		mdio	MIO 53
Enet 1			Disabled
USB 0			MIO 28 .. 39
		clk	MIO 36
		dir	MIO 29
		stp	MIO 30
		nxt	MIO 31
		data[0]	MIO 32
		data[1]	MIO 33
		data[2]	MIO 34
		data[3]	MIO 35
		data[4]	MIO 28
		data[5]	MIO 37
		data[6]	MIO 38
		data[7]	MIO 39
USB 1			Disabled
SD 0			MIO 40 .. 45
	CD		MIO 47
	WP		MIO 46
	Power		Disabled
SD 1			Disabled
UART 0			Disabled
UART 1			MIO 48 .. 49
		rx	MIO 49
		tx	MIO 48
	Modem Signals		Disabled
I2C 0			Disabled
I2C 1			Disabled
SPI 0			Disabled
SPI 1			Disabled
CAN 0			Disabled
CAN 1			Disabled
Trace			Disabled
Timer 0			EMIO
		clk_in	EMIO
		wave_out	EMIO
Timer 1			Disabled
Watchdog			Disabled
PJTAG			Disabled
GPIO			MIO
Mode			Disabled
VCfg			Disabled

Go To TOP

DDR Memory information

DDR Controller Configuration

Parameter	Value
Enable DDR	1
Memory Type	DDR 3
Memory Part	MT41J128M16 HA-15E
DRAM bus width	32 Bit
ECC	Disabled
BURST Length (lppdr only)	8
Internal Vref	1
Operating Frequency (MHz)	533.333313
HIGH temperature	Normal (0-85)

Memory Part Configuration

Parameter	Value
DRAM IC bus width	16 Bits
DRAM Device Capacity	2048 MBits
Speed Bin	DDR3_1066F
BANK Address Count	3
ROW Address Count	14
COLUMN Address Count	10
CAS Latency	7
CAS Write Latency	6
RAS to CAS Delay	7
RECHARGE Time	7
tRC (ns )	49.5
tRASmin ( ns )	36.0
tFAW	45.0
ADDITIVE Latency	0

Training/Board Details

Parameter	Value
Write levelling	1
Read gate	1
Read data eye	1
DQS to Clock delay [0] (ns)	0.025
DQS to Clock delay [1] (ns)	0.028
DQS to Clock delay [2] (ns)	-0.009
DQS to Clock delay [3] (ns)	-0.061
Board delay [0] (ns)	0.41
Board delay [1] (ns)	0.411
Board delay [2] (ns)	0.341
Board delay [3] (ns)	0.358

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ps7_pll_init_data_3_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

PLL SLCR REGISTERS

ARM PLL INIT

Register : ARM_PLL_CFG @ 0XF8000110

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 fa fa000

ARM_PLL_CFG @ 0XF8000110 3ffff0 fa220

UPDATE FB_DIV

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 28 28000

ARM_PLL_CTRL @ 0XF8000100 7f000 28000

BY PASS PLL

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

ARM_PLL_CTRL @ 0XF8000100 10 10

ASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

ARM_PLL_CTRL @ 0XF8000100 1 1

DEASSERT RESET

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

ARM_PLL_CTRL @ 0XF8000100 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

ARM_PLL_LOCK 0:0 1 1 1

PLL_STATUS @ 0XF800010C 1 1

REMOVE PLL BY PASS

Register : ARM_PLL_CTRL @ 0XF8000100

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

ARM_PLL_CTRL @ 0XF8000100 10 0

Bitfield	Bits	Mask	Value	Shifted Value
SRCSEL	5:4	30	0	0
DIVISOR	13:8	3f00	2	200
CPU_6OR4XCLKACT	24:24	1000000	1	1000000
CPU_3OR2XCLKACT	25:25	2000000	1	2000000
CPU_2XCLKACT	26:26	4000000	1	4000000
CPU_1XCLKACT	27:27	8000000	1	8000000
CPU_PERI_CLKACT	28:28	10000000	1	10000000
ARM_CLK_CTRL @ 0XF8000120		1f003f30		1f000200

DDR PLL INIT

Register : DDR_PLL_CFG @ 0XF8000114

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 2 20

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 12c 12c000

DDR_PLL_CFG @ 0XF8000114 3ffff0 12c220

UPDATE FB_DIV

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 20 20000

DDR_PLL_CTRL @ 0XF8000104 7f000 20000

BY PASS PLL

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

DDR_PLL_CTRL @ 0XF8000104 10 10

ASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

DDR_PLL_CTRL @ 0XF8000104 1 1

DEASSERT RESET

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

DDR_PLL_CTRL @ 0XF8000104 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

DDR_PLL_LOCK 1:1 2 1 2

PLL_STATUS @ 0XF800010C 2 2

REMOVE PLL BY PASS

Register : DDR_PLL_CTRL @ 0XF8000104

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

DDR_PLL_CTRL @ 0XF8000104 10 0

Register : DDR_CLK_CTRL @ 0XF8000124

Bitfield Bits Mask Value Shifted Value

DDR_3XCLKACT 0:0 1 1 1

DDR_2XCLKACT 1:1 2 1 2

DDR_3XCLK_DIVISOR 25:20 3f00000 2 200000

DDR_2XCLK_DIVISOR 31:26 fc000000 3 c000000

DDR_CLK_CTRL @ 0XF8000124 fff00003 c200003

IO PLL INIT

Register : IO_PLL_CFG @ 0XF8000118

Bitfield Bits Mask Value Shifted Value

PLL_RES 7:4 f0 c c0

PLL_CP 11:8 f00 2 200

LOCK_CNT 21:12 3ff000 145 145000

IO_PLL_CFG @ 0XF8000118 3ffff0 1452c0

UPDATE FB_DIV

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_FDIV 18:12 7f000 1e 1e000

IO_PLL_CTRL @ 0XF8000108 7f000 1e000

BY PASS PLL

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 1 10

IO_PLL_CTRL @ 0XF8000108 10 10

ASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 1 1

IO_PLL_CTRL @ 0XF8000108 1 1

DEASSERT RESET

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_RESET 0:0 1 0 0

IO_PLL_CTRL @ 0XF8000108 1 0

CHECK PLL STATUS

Register : PLL_STATUS @ 0XF800010C

Bitfield Bits Mask Value Shifted Value

IO_PLL_LOCK 2:2 4 1 4

PLL_STATUS @ 0XF800010C 4 4

REMOVE PLL BY PASS

Register : IO_PLL_CTRL @ 0XF8000108

Bitfield Bits Mask Value Shifted Value

PLL_BYPASS_FORCE 4:4 10 0 0

IO_PLL_CTRL @ 0XF8000108 10 0

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_clock_init_data_3_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

CLOCK CONTROL SLCR REGISTERS

Register : DCI_CLK_CTRL @ 0XF8000128

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

DIVISOR0 13:8 3f00 23 2300

DIVISOR1 25:20 3f00000 3 300000

DCI_CLK_CTRL @ 0XF8000128 3f03f01 302301
Register : GEM0_RCLK_CTRL @ 0XF8000138

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 4:4 10 0 0

GEM0_RCLK_CTRL @ 0XF8000138 11 1
Register : GEM0_CLK_CTRL @ 0XF8000140

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 6:4 70 0 0

DIVISOR 13:8 3f00 8 800

DIVISOR1 25:20 3f00000 1 100000

GEM0_CLK_CTRL @ 0XF8000140 3f03f71 100801
Register : LQSPI_CLK_CTRL @ 0XF800014C

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

LQSPI_CLK_CTRL @ 0XF800014C 3f31 501
Register : SDIO_CLK_CTRL @ 0XF8000150

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 1 1

CLKACT1 1:1 2 0 0

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

SDIO_CLK_CTRL @ 0XF8000150 3f33 1401
Register : UART_CLK_CTRL @ 0XF8000154

Bitfield Bits Mask Value Shifted Value

CLKACT0 0:0 1 0 0

CLKACT1 1:1 2 1 2

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 14 1400

UART_CLK_CTRL @ 0XF8000154 3f33 1402
Register : PCAP_CLK_CTRL @ 0XF8000168

Bitfield Bits Mask Value Shifted Value

CLKACT 0:0 1 1 1

SRCSEL 5:4 30 0 0

DIVISOR 13:8 3f00 5 500

PCAP_CLK_CTRL @ 0XF8000168 3f31 501
Register : FPGA0_CLK_CTRL @ 0XF8000170

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 a a00

DIVISOR1 25:20 3f00000 1 100000

FPGA0_CLK_CTRL @ 0XF8000170 3f03f30 100a00
Register : FPGA1_CLK_CTRL @ 0XF8000180

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 7 700

DIVISOR1 25:20 3f00000 1 100000

FPGA1_CLK_CTRL @ 0XF8000180 3f03f30 100700
Register : FPGA2_CLK_CTRL @ 0XF8000190

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA2_CLK_CTRL @ 0XF8000190 3f03f30 101400
Register : FPGA3_CLK_CTRL @ 0XF80001A0

Bitfield Bits Mask Value Shifted Value

SRCSEL 5:4 30 0 0

DIVISOR0 13:8 3f00 14 1400

DIVISOR1 25:20 3f00000 1 100000

FPGA3_CLK_CTRL @ 0XF80001A0 3f03f30 101400
Register : CLK_621_TRUE @ 0XF80001C4

Bitfield Bits Mask Value Shifted Value

CLK_621_TRUE 0:0 1 1 1

CLK_621_TRUE @ 0XF80001C4 1 1

Bitfield	Bits	Mask	Value	Shifted Value
DMA_CPU_2XCLKACT	0:0	1	1	1
USB0_CPU_1XCLKACT	2:2	4	1	4
USB1_CPU_1XCLKACT	3:3	8	1	8
GEM0_CPU_1XCLKACT	6:6	40	1	40
GEM1_CPU_1XCLKACT	7:7	80	0	0
SDI0_CPU_1XCLKACT	10:10	400	1	400
SDI1_CPU_1XCLKACT	11:11	800	0	0
SPI0_CPU_1XCLKACT	14:14	4000	0	0
SPI1_CPU_1XCLKACT	15:15	8000	0	0
CAN0_CPU_1XCLKACT	16:16	10000	0	0
CAN1_CPU_1XCLKACT	17:17	20000	0	0
I2C0_CPU_1XCLKACT	18:18	40000	1	40000
I2C1_CPU_1XCLKACT	19:19	80000	1	80000
UART0_CPU_1XCLKACT	20:20	100000	0	0
UART1_CPU_1XCLKACT	21:21	200000	1	200000
GPIO_CPU_1XCLKACT	22:22	400000	1	400000
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000
APER_CLK_CTRL @ 0XF800012C		1ffcccd		1ec044d

THIS SHOULD BE BLANK

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_ddr_init_data_3_0

DDR INITIALIZATION

LOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	0	0
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		80

Register : Two_rank_cfg @ 0XF8006004

Bitfield Bits Mask Value Shifted Value

reg_ddrc_t_rfc_nom_x32 11:0 fff 81 81

reserved_reg_ddrc_active_ranks 13:12 3000 1 1000

reg_ddrc_addrmap_cs_bit0 18:14 7c000 0 0

Two_rank_cfg @ 0XF8006004 7ffff 1081

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_hpr_min_non_critical_x32	10:0	7ff	f	f
reg_ddrc_hpr_max_starve_x32	21:11	3ff800	f	7800
reg_ddrc_hpr_xact_run_length	25:22	3c00000	f	3c00000
HPR_reg @ 0XF8006008		3ffffff		3c0780f

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_lpr_min_non_critical_x32	10:0	7ff	1	1
reg_ddrc_lpr_max_starve_x32	21:11	3ff800	2	1000
reg_ddrc_lpr_xact_run_length	25:22	3c00000	8	2000000
LPR_reg @ 0XF800600C		3ffffff		2001001

Register : WR_reg @ 0XF8006010

Bitfield Bits Mask Value Shifted Value

reg_ddrc_w_min_non_critical_x32 10:0 7ff 1 1

reg_ddrc_w_xact_run_length 14:11 7800 8 4000

reg_ddrc_w_max_starve_x32 25:15 3ff8000 2 10000

WR_reg @ 0XF8006010 3ffffff 14001
Register : DRAM_param_reg0 @ 0XF8006014

Bitfield Bits Mask Value Shifted Value

reg_ddrc_t_rc 5:0 3f 1b 1b

reg_ddrc_t_rfc_min 13:6 3fc0 56 1580

reg_ddrc_post_selfref_gap_x32 20:14 1fc000 10 40000

DRAM_param_reg0 @ 0XF8006014 1fffff 4159b

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_wr2pre	4:0	1f	12	12
reg_ddrc_powerdown_to_x32	9:5	3e0	6	c0
reg_ddrc_t_faw	15:10	fc00	18	6000
reg_ddrc_t_ras_max	21:16	3f0000	24	240000
reg_ddrc_t_ras_min	26:22	7c00000	14	5000000
reg_ddrc_t_cke	31:28	f0000000	4	40000000
DRAM_param_reg1 @ 0XF8006018		f7ffffff		452460d2

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_write_latency	4:0	1f	5	5
reg_ddrc_rd2wr	9:5	3e0	7	e0
reg_ddrc_wr2rd	14:10	7c00	e	3800
reg_ddrc_t_xp	19:15	f8000	4	20000
reg_ddrc_pad_pd	22:20	700000	0	0
reg_ddrc_rd2pre	27:23	f800000	4	2000000
reg_ddrc_t_rcd	31:28	f0000000	7	70000000
DRAM_param_reg2 @ 0XF800601C		ffffffff		720238e5

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_ccd	4:2	1c	4	10
reg_ddrc_t_rrd	7:5	e0	6	c0
reg_ddrc_refresh_margin	11:8	f00	2	200
reg_ddrc_t_rp	15:12	f000	7	7000
reg_ddrc_refresh_to_x32	20:16	1f0000	8	80000
reg_ddrc_mobile	22:22	400000	0	0
reg_ddrc_en_dfi_dram_clk_disable	23:23	800000	0	0
reg_ddrc_read_latency	28:24	1f000000	7	7000000
reg_phy_mode_ddr1_ddr2	29:29	20000000	1	20000000
reg_ddrc_dis_pad_pd	30:30	40000000	0	0
DRAM_param_reg3 @ 0XF8006020		7fdffffc		270872d0

Bitfield	Bits	Mask	Value
reg_ddrc_en_2t_timing_mode	0:0	1	0
reg_ddrc_prefer_write	1:1	2	0
reg_ddrc_mr_wr	6:6	40	0
reg_ddrc_mr_addr	8:7	180	0
reg_ddrc_mr_data	24:9	1fffe00	0
ddrc_reg_mr_wr_busy	25:25	2000000	0
reg_ddrc_mr_type	26:26	4000000	0
reg_ddrc_mr_rdata_valid	27:27	8000000	0
DRAM_param_reg4 @ 0XF8006024		fffffc3

Register : DRAM_init_param @ 0XF8006028

Bitfield Bits Mask Value Shifted Value

reg_ddrc_final_wait_x32 6:0 7f 7 7

reg_ddrc_pre_ocd_x32 10:7 780 0 0

reg_ddrc_t_mrd 13:11 3800 4 2000

DRAM_init_param @ 0XF8006028 3fff 2007
Register : DRAM_EMR_reg @ 0XF800602C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_emr2 15:0 ffff 8 8

reg_ddrc_emr3 31:16 ffff0000 0 0

DRAM_EMR_reg @ 0XF800602C ffffffff 8
Register : DRAM_EMR_MR_reg @ 0XF8006030

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr 15:0 ffff 930 930

reg_ddrc_emr 31:16 ffff0000 4 40000

DRAM_EMR_MR_reg @ 0XF8006030 ffffffff 40930

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_burst_rdwr	3:0	f	4	4
reg_ddrc_pre_cke_x1024	13:4	3ff0	69	690
reg_ddrc_post_cke_x1024	25:16	3ff0000	1	10000
reg_ddrc_burstchop	28:28	10000000	0	0
DRAM_burst8_rdwr @ 0XF8006034		13ff3fff		10694

Register : DRAM_disable_DQ @ 0XF8006038

Bitfield Bits Mask Value Shifted Value

reg_ddrc_force_low_pri_n 0:0 1 0 0

reg_ddrc_dis_dq 1:1 2 0 0

DRAM_disable_DQ @ 0XF8006038 3 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_bank_b0	3:0	f	7	7
reg_ddrc_addrmap_bank_b1	7:4	f0	7	70
reg_ddrc_addrmap_bank_b2	11:8	f00	7	700
reg_ddrc_addrmap_col_b5	15:12	f000	0	0
reg_ddrc_addrmap_col_b6	19:16	f0000	0	0
DRAM_addr_map_bank @ 0XF800603C		fffff		777

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_col_b2	3:0	f	0	0
reg_ddrc_addrmap_col_b3	7:4	f0	0	0
reg_ddrc_addrmap_col_b4	11:8	f00	0	0
reg_ddrc_addrmap_col_b7	15:12	f000	0	0
reg_ddrc_addrmap_col_b8	19:16	f0000	0	0
reg_ddrc_addrmap_col_b9	23:20	f00000	f	f00000
reg_ddrc_addrmap_col_b10	27:24	f000000	f	f000000
reg_ddrc_addrmap_col_b11	31:28	f0000000	f	f0000000
DRAM_addr_map_col @ 0XF8006040		ffffffff		fff00000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_addrmap_row_b0	3:0	f	6	6
reg_ddrc_addrmap_row_b1	7:4	f0	6	60
reg_ddrc_addrmap_row_b2_11	11:8	f00	6	600
reg_ddrc_addrmap_row_b12	15:12	f000	6	6000
reg_ddrc_addrmap_row_b13	19:16	f0000	6	60000
reg_ddrc_addrmap_row_b14	23:20	f00000	f	f00000
reg_ddrc_addrmap_row_b15	27:24	f000000	f	f000000
DRAM_addr_map_row @ 0XF8006044		fffffff		ff66666

Register : DRAM_ODT_reg @ 0XF8006048

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_local_odt 13:12 3000 0 0

reg_phy_wr_local_odt 15:14 c000 3 c000

reg_phy_idle_local_odt 17:16 30000 3 30000

DRAM_ODT_reg @ 0XF8006048 3f000 3c000

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_rd_cmd_to_data	3:0	f	0	0
reg_phy_wr_cmd_to_data	7:4	f0	0	0
reg_phy_rdc_we_to_re_delay	11:8	f00	8	800
reg_phy_rdc_fifo_rst_disable	15:15	8000	0	0
reg_phy_use_fixed_re	16:16	10000	1	10000
reg_phy_rdc_fifo_rst_err_cnt_clr	17:17	20000	0	0
reg_phy_dis_phy_ctrl_rstn	18:18	40000	0	0
reg_phy_clk_stall_level	19:19	80000	0	0
reg_phy_gatelvl_num_of_dq0	27:24	f000000	7	7000000
reg_phy_wrlvl_num_of_dq0	31:28	f0000000	7	70000000
phy_cmd_timeout_rddata_cpt @ 0XF8006050		ff0f8fff		77010800

Register : DLL_calib @ 0XF8006058

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dis_dll_calib 16:16 10000 0 0

DLL_calib @ 0XF8006058 10000 0
Register : ODT_delay_hold @ 0XF800605C

Bitfield Bits Mask Value Shifted Value

reg_ddrc_rd_odt_delay 3:0 f 3 3

reg_ddrc_wr_odt_delay 7:4 f0 0 0

reg_ddrc_rd_odt_hold 11:8 f00 0 0

reg_ddrc_wr_odt_hold 15:12 f000 5 5000

ODT_delay_hold @ 0XF800605C ffff 5003

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_pageclose	0:0	1	0	0
reg_ddrc_lpr_num_entries	6:1	7e	1f	3e
reg_ddrc_auto_pre_en	7:7	80	0	0
reg_ddrc_refresh_update_level	8:8	100	0	0
reg_ddrc_dis_wc	9:9	200	0	0
reg_ddrc_dis_collision_page_opt	10:10	400	0	0
reg_ddrc_selfref_en	12:12	1000	0	0
ctrl_reg1 @ 0XF8006060		17ff		3e

Register : ctrl_reg2 @ 0XF8006064

Bitfield Bits Mask Value Shifted Value

reg_ddrc_go2critical_hysteresis 12:5 1fe0 0 0

reg_arb_go2critical_en 17:17 20000 1 20000

ctrl_reg2 @ 0XF8006064 21fe0 20000
Register : ctrl_reg3 @ 0XF8006068

Bitfield Bits Mask Value Shifted Value

reg_ddrc_wrlvl_ww 7:0 ff 41 41

reg_ddrc_rdlvl_rr 15:8 ff00 41 4100

reg_ddrc_dfi_t_wlmrd 25:16 3ff0000 28 280000

ctrl_reg3 @ 0XF8006068 3ffffff 284141
Register : ctrl_reg4 @ 0XF800606C

Bitfield Bits Mask Value Shifted Value

dfi_t_ctrlupd_interval_min_x1024 7:0 ff 10 10

dfi_t_ctrlupd_interval_max_x1024 15:8 ff00 16 1600

ctrl_reg4 @ 0XF800606C ffff 1610

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dfi_t_ctrl_delay	3:0	f	1	1
reg_ddrc_dfi_t_dram_clk_disable	7:4	f0	1	10
reg_ddrc_dfi_t_dram_clk_enable	11:8	f00	1	100
reg_ddrc_t_cksre	15:12	f000	6	6000
reg_ddrc_t_cksrx	19:16	f0000	6	60000
reg_ddrc_t_ckesr	25:20	3f00000	4	400000
ctrl_reg5 @ 0XF8006078		3ffffff		466111

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_ckpde	3:0	f	2	2
reg_ddrc_t_ckpdx	7:4	f0	2	20
reg_ddrc_t_ckdpde	11:8	f00	2	200
reg_ddrc_t_ckdpdx	15:12	f000	2	2000
reg_ddrc_t_ckcsx	19:16	f0000	3	30000
ctrl_reg6 @ 0XF800607C		fffff		32222

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dis_auto_zq	0:0	1	0	0
reg_ddrc_ddr3	1:1	2	1	2
reg_ddrc_t_mod	11:2	ffc	200	800
reg_ddrc_t_zq_long_nop	21:12	3ff000	200	200000
reg_ddrc_t_zq_short_nop	31:22	ffc00000	40	10000000
CHE_T_ZQ @ 0XF80060A4		ffffffff		10200802

Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8

Bitfield Bits Mask Value Shifted Value

t_zq_short_interval_x1024 19:0 fffff cb73 cb73

dram_rstn_x1024 27:20 ff00000 69 6900000

CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8 fffffff 690cb73
Register : deep_pwrdwn_reg @ 0XF80060AC

Bitfield Bits Mask Value Shifted Value

deeppowerdown_en 0:0 1 0 0

deeppowerdown_to_x1024 8:1 1fe ff 1fe

deep_pwrdwn_reg @ 0XF80060AC 1ff 1fe

Bitfield	Bits	Mask	Value	Shifted Value
dfi_wrlvl_max_x1024	11:0	fff	fff	fff
dfi_rdlvl_max_x1024	23:12	fff000	fff	fff000
ddrc_reg_twrlvl_max_error	24:24	1000000	0	0
ddrc_reg_trdlvl_max_error	25:25	2000000	0	0
reg_ddrc_dfi_wr_level_en	26:26	4000000	1	4000000
reg_ddrc_dfi_rd_dqs_gate_level	27:27	8000000	1	8000000
reg_ddrc_dfi_rd_data_eye_train	28:28	10000000	1	10000000
reg_2c @ 0XF80060B0		1fffffff		1cffffff

Register : reg_2d @ 0XF80060B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_skip_ocd 9:9 200 1 200

reg_2d @ 0XF80060B4 200 200
Register : dfi_timing @ 0XF80060B8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_dfi_t_rddata_en 4:0 1f 6 6

reg_ddrc_dfi_t_ctrlup_min 14:5 7fe0 3 60

reg_ddrc_dfi_t_ctrlup_max 24:15 1ff8000 40 200000

dfi_timing @ 0XF80060B8 1ffffff 200066
Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4

Bitfield Bits Mask Value Shifted Value

Clear_Uncorrectable_DRAM_ECC_error 0:0 1 0 0

Clear_Correctable_DRAM_ECC_error 1:1 2 0 0

CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4 3 0
Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8

Bitfield Bits Mask Value Shifted Value

CORR_ECC_LOG_VALID 0:0 1 0 0

ECC_CORRECTED_BIT_NUM 7:1 fe 0 0

CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8 ff 0
Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC

Bitfield Bits Mask Value Shifted Value

UNCORR_ECC_LOG_VALID 0:0 1 0 0

CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC 1 0
Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0

Bitfield Bits Mask Value Shifted Value

STAT_NUM_CORR_ERR 15:8 ff00 0 0

STAT_NUM_UNCORR_ERR 7:0 ff 0 0

CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0 ffff 0
Register : ECC_scrub @ 0XF80060F4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_ecc_mode 2:0 7 0 0

reg_ddrc_dis_scrub 3:3 8 1 8

ECC_scrub @ 0XF80060F4 f 8
Register : phy_rcvr_enable @ 0XF8006114

Bitfield Bits Mask Value Shifted Value

reg_phy_dif_on 3:0 f 0 0

reg_phy_dif_off 7:4 f0 0 0

phy_rcvr_enable @ 0XF8006114 ff 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006118		7fffffcf		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF800611C		7fffffcf		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006120		7fffffcf		40000001

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_data_slice_in_use	0:0	1	1	1
reg_phy_rdlvl_inc_mode	1:1	2	0	0
reg_phy_gatelvl_inc_mode	2:2	4	0	0
reg_phy_wrlvl_inc_mode	3:3	8	0	0
reg_phy_bist_shift_dq	14:6	7fc0	0	0
reg_phy_bist_err_clr	23:15	ff8000	0	0
reg_phy_dq_offset	30:24	7f000000	40	40000000
PHY_Config @ 0XF8006124		7fffffcf		40000001

Register : phy_init_ratio @ 0XF800612C

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 cf 33c00

phy_init_ratio @ 0XF800612C fffff 33c03
Register : phy_init_ratio @ 0XF8006130

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 3 3

reg_phy_gatelvl_init_ratio 19:10 ffc00 d0 34000

phy_init_ratio @ 0XF8006130 fffff 34003
Register : phy_init_ratio @ 0XF8006134

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 bd 2f400

phy_init_ratio @ 0XF8006134 fffff 2f400
Register : phy_init_ratio @ 0XF8006138

Bitfield Bits Mask Value Shifted Value

reg_phy_wrlvl_init_ratio 9:0 3ff 0 0

reg_phy_gatelvl_init_ratio 19:10 ffc00 c1 30400

phy_init_ratio @ 0XF8006138 fffff 30400
Register : phy_rd_dqs_cfg @ 0XF8006140

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006140 fffff 35
Register : phy_rd_dqs_cfg @ 0XF8006144

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006144 fffff 35
Register : phy_rd_dqs_cfg @ 0XF8006148

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF8006148 fffff 35
Register : phy_rd_dqs_cfg @ 0XF800614C

Bitfield Bits Mask Value Shifted Value

reg_phy_rd_dqs_slave_ratio 9:0 3ff 35 35

reg_phy_rd_dqs_slave_force 10:10 400 0 0

reg_phy_rd_dqs_slave_delay 19:11 ff800 0 0

phy_rd_dqs_cfg @ 0XF800614C fffff 35
Register : phy_wr_dqs_cfg @ 0XF8006154

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006154 fffff 83
Register : phy_wr_dqs_cfg @ 0XF8006158

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 83 83

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006158 fffff 83
Register : phy_wr_dqs_cfg @ 0XF800615C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 7f 7f

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF800615C fffff 7f
Register : phy_wr_dqs_cfg @ 0XF8006160

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_dqs_slave_ratio 9:0 3ff 78 78

reg_phy_wr_dqs_slave_force 10:10 400 0 0

reg_phy_wr_dqs_slave_delay 19:11 ff800 0 0

phy_wr_dqs_cfg @ 0XF8006160 fffff 78
Register : phy_we_cfg @ 0XF8006168

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 124 124

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006168 1fffff 124
Register : phy_we_cfg @ 0XF800616C

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 125 125

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF800616C 1fffff 125
Register : phy_we_cfg @ 0XF8006170

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 112 112

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006170 1fffff 112
Register : phy_we_cfg @ 0XF8006174

Bitfield Bits Mask Value Shifted Value

reg_phy_fifo_we_slave_ratio 10:0 7ff 116 116

reg_phy_fifo_we_in_force 11:11 800 0 0

reg_phy_fifo_we_in_delay 20:12 1ff000 0 0

phy_we_cfg @ 0XF8006174 1fffff 116
Register : wr_data_slv @ 0XF800617C

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF800617C fffff c3
Register : wr_data_slv @ 0XF8006180

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff c3 c3

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006180 fffff c3
Register : wr_data_slv @ 0XF8006184

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff bf bf

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006184 fffff bf
Register : wr_data_slv @ 0XF8006188

Bitfield Bits Mask Value Shifted Value

reg_phy_wr_data_slave_ratio 9:0 3ff b8 b8

reg_phy_wr_data_slave_force 10:10 400 0 0

reg_phy_wr_data_slave_delay 19:11 ff800 0 0

wr_data_slv @ 0XF8006188 fffff b8

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_bl2	1:1	2	0	0
reg_phy_at_spd_atpg	2:2	4	0	0
reg_phy_bist_enable	3:3	8	0	0
reg_phy_bist_force_err	4:4	10	0	0
reg_phy_bist_mode	6:5	60	0	0
reg_phy_invert_clkout	7:7	80	1	80
reg_phy_sel_logic	9:9	200	0	0
reg_phy_ctrl_slave_ratio	19:10	ffc00	100	40000
reg_phy_ctrl_slave_force	20:20	100000	0	0
reg_phy_ctrl_slave_delay	27:21	fe00000	0	0
reg_phy_lpddr	29:29	20000000	0	0
reg_phy_cmd_latency	30:30	40000000	0	0
reg_64 @ 0XF8006190		6ffffefe		40080

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wr_rl_delay	4:0	1f	2	2
reg_phy_rd_rl_delay	9:5	3e0	4	80
reg_phy_dll_lock_diff	13:10	3c00	f	3c00
reg_phy_use_wr_level	14:14	4000	1	4000
reg_phy_use_rd_dqs_gate_level	15:15	8000	1	8000
reg_phy_use_rd_data_eye_level	16:16	10000	1	10000
reg_phy_dis_calib_rst	17:17	20000	0	0
reg_phy_ctrl_slave_delay	19:18	c0000	0	0
reg_65 @ 0XF8006194		fffff		1fc82

Register : page_mask @ 0XF8006204

Bitfield Bits Mask Value Shifted Value

reg_arb_page_addr_mask 31:0 0 0 0

page_mask @ 0XF8006204 0 0

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
axi_priority_wr_port @ 0XF8006208		703ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
axi_priority_wr_port @ 0XF800620C		703ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
axi_priority_wr_port @ 0XF8006210		703ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_wr_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_wr_portn	16:16	10000	0	0
reg_arb_disable_urgent_wr_portn	17:17	20000	0	0
reg_arb_dis_page_match_wr_portn	18:18	40000	0	0
axi_priority_wr_port @ 0XF8006214		703ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006218		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF800621C		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006220		f03ff		3ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_arb_pri_rd_portn	9:0	3ff	3ff	3ff
reg_arb_disable_aging_rd_portn	16:16	10000	0	0
reg_arb_disable_urgent_rd_portn	17:17	20000	0	0
reg_arb_dis_page_match_rd_portn	18:18	40000	0	0
reg_arb_set_hpr_rd_portn	19:19	80000	0	0
axi_priority_rd_port @ 0XF8006224		f03ff		3ff

Register : lpddr_ctrl0 @ 0XF80062A8

Bitfield Bits Mask Value Shifted Value

reg_ddrc_lpddr2 0:0 1 0 0

reg_ddrc_derate_enable 2:2 4 0 0

reg_ddrc_mr4_margin 11:4 ff0 0 0

lpddr_ctrl0 @ 0XF80062A8 ff5 0
Register : lpddr_ctrl1 @ 0XF80062AC

Bitfield Bits Mask Value Shifted Value

reg_ddrc_mr4_read_interval 31:0 0 0 0

lpddr_ctrl1 @ 0XF80062AC 0 0
Register : lpddr_ctrl2 @ 0XF80062B0

Bitfield Bits Mask Value Shifted Value

reg_ddrc_min_stable_clock_x1 3:0 f 5 5

reg_ddrc_idle_after_reset_x32 11:4 ff0 12 120

reg_ddrc_t_mrw 21:12 3ff000 5 5000

lpddr_ctrl2 @ 0XF80062B0 3fffff 5125
Register : lpddr_ctrl3 @ 0XF80062B4

Bitfield Bits Mask Value Shifted Value

reg_ddrc_max_auto_init_x1024 7:0 ff a8 a8

reg_ddrc_dev_zqinit_x32 17:8 3ff00 12 1200

lpddr_ctrl3 @ 0XF80062B4 3ffff 12a8

POLL ON DCI STATUS

Register : DDRIOB_DCI_STATUS @ 0XF8000B74

Bitfield Bits Mask Value Shifted Value

DONE 13:13 2000 1 2000

DDRIOB_DCI_STATUS @ 0XF8000B74 2000 2000

UNLOCK DDR

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_soft_rstb	0:0	1	1	1
reg_ddrc_powerdown_en	1:1	2	0	0
reg_ddrc_data_bus_width	3:2	c	0	0
reg_ddrc_burst8_refresh	6:4	70	0	0
reg_ddrc_rdwr_idle_gap	13:7	3f80	1	80
reg_ddrc_dis_rd_bypass	14:14	4000	0	0
reg_ddrc_dis_act_bypass	15:15	8000	0	0
reg_ddrc_dis_auto_refresh	16:16	10000	0	0
ddrc_ctrl @ 0XF8006000		1ffff		81

CHECK DDR STATUS

Register : mode_sts_reg @ 0XF8006054

Bitfield Bits Mask Value Shifted Value

ddrc_reg_operating_mode 2:0 7 1 1

mode_sts_reg @ 0XF8006054 7 1

ps7_mio_init_data_3_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

OCM REMAPPING

DDRIOB SETTINGS

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	0	0
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCI_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR0 @ 0XF8000B40		ffe		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	0	0
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCI_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_ADDR1 @ 0XF8000B44		ffe		600

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	1	2
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCI_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA0 @ 0XF8000B48		ffe		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	1	2
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCI_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DATA1 @ 0XF8000B4C		ffe		672

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	2	4
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCI_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF0 @ 0XF8000B50		ffe		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	2	4
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	1	10
DCI_TYPE	6:5	60	3	60
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_DIFF1 @ 0XF8000B54		ffe		674

Bitfield	Bits	Mask	Value	Shifted Value
INP_TYPE	2:1	6	0	0
DCI_UPDATE_B	3:3	8	0	0
TERM_EN	4:4	10	0	0
DCI_TYPE	6:5	60	0	0
IBUF_DISABLE_MODE	7:7	80	0	0
TERM_DISABLE_MODE	8:8	100	0	0
OUTPUT_EN	10:9	600	3	600
PULLUP_EN	11:11	800	0	0
DDRIOB_CLOCK @ 0XF8000B58		ffe		600

Register : DDRIOB_DDR_CTRL @ 0XF8000B6C

Bitfield Bits Mask Value Shifted Value

VREF_INT_EN 0:0 1 1 1

VREF_SEL 4:1 1e 4 8

VREF_EXT_EN 6:5 60 0 0

REFIO_EN 9:9 200 1 200

DDRIOB_DDR_CTRL @ 0XF8000B6C 27f 209

ASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 1 1

DDRIOB_DCI_CTRL @ 0XF8000B70 1 1

DEASSERT RESET

Register : DDRIOB_DCI_CTRL @ 0XF8000B70

Bitfield Bits Mask Value Shifted Value

RESET 0:0 1 0 0

DDRIOB_DCI_CTRL @ 0XF8000B70 1 0

Bitfield	Bits	Mask	Value	Shifted Value
RESET	0:0	1	1	1
ENABLE	1:1	2	1	2
NREF_OPT1	7:6	c0	0	0
NREF_OPT2	10:8	700	0	0
NREF_OPT4	13:11	3800	1	800
PREF_OPT2	19:17	e0000	0	0
UPDATE_CONTROL	20:20	100000	0	0
DDRIOB_DCI_CTRL @ 0XF8000B70		1e3fc3		803

MIO PROGRAMMING

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_00 @ 0XF8000700		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_01 @ 0XF8000704		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_02 @ 0XF8000708		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_03 @ 0XF800070C		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_04 @ 0XF8000710		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_05 @ 0XF8000714		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_06 @ 0XF8000718		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_07 @ 0XF800071C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_08 @ 0XF8000720		3fff		702

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_09 @ 0XF8000724		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_10 @ 0XF8000728		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_11 @ 0XF800072C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_12 @ 0XF8000730		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_13 @ 0XF8000734		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_14 @ 0XF8000738		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	3	600
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_15 @ 0XF800073C		3fff		600

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_16 @ 0XF8000740		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_17 @ 0XF8000744		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_18 @ 0XF8000748		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_19 @ 0XF800074C		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_20 @ 0XF8000750		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_21 @ 0XF8000754		3fff		302

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_22 @ 0XF8000758		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_23 @ 0XF800075C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_24 @ 0XF8000760		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_25 @ 0XF8000764		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_26 @ 0XF8000768		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	1	2
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_27 @ 0XF800076C		3fff		303

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_28 @ 0XF8000770		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_29 @ 0XF8000774		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_30 @ 0XF8000778		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_31 @ 0XF800077C		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_32 @ 0XF8000780		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_33 @ 0XF8000784		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_34 @ 0XF8000788		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_35 @ 0XF800078C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_36 @ 0XF8000790		3fff		305

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_37 @ 0XF8000794		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_38 @ 0XF8000798		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	1	4
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_39 @ 0XF800079C		3fff		304

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_40 @ 0XF80007A0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_41 @ 0XF80007A4		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_42 @ 0XF80007A8		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_43 @ 0XF80007AC		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_44 @ 0XF80007B0		3fff		380

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	1	100
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_45 @ 0XF80007B4		3fff		380

Register : MIO_PIN_46 @ 0XF80007B8

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_46 @ 0XF80007B8 3f01 201
Register : MIO_PIN_47 @ 0XF80007BC

Bitfield Bits Mask Value Shifted Value

TRI_ENABLE 0:0 1 1 1

Speed 8:8 100 0 0

IO_Type 11:9 e00 1 200

PULLUP 12:12 1000 0 0

DisableRcvr 13:13 2000 0 0

MIO_PIN_47 @ 0XF80007BC 3f01 201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_48 @ 0XF80007C0		3fff		2e0

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	7	e0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_49 @ 0XF80007C4		3fff		2e1

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_50 @ 0XF80007C8		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	1	1
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	0	0
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_51 @ 0XF80007CC		3fff		201

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_52 @ 0XF80007D0		3fff		280

Bitfield	Bits	Mask	Value	Shifted Value
TRI_ENABLE	0:0	1	0	0
L0_SEL	1:1	2	0	0
L1_SEL	2:2	4	0	0
L2_SEL	4:3	18	0	0
L3_SEL	7:5	e0	4	80
Speed	8:8	100	0	0
IO_Type	11:9	e00	1	200
PULLUP	12:12	1000	0	0
DisableRcvr	13:13	2000	0	0
MIO_PIN_53 @ 0XF80007D4		3fff		280

Register : SD0_WP_CD_SEL @ 0XF8000830

Bitfield Bits Mask Value Shifted Value

SDIO0_WP_SEL 5:0 3f 2e 2e

SDIO0_CD_SEL 21:16 3f0000 2f 2f0000

SD0_WP_CD_SEL @ 0XF8000830 3f003f 2f002e

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

ps7_peripherals_init_data_3_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register : DDRIOB_DATA0 @ 0XF8000B48

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA0 @ 0XF8000B48 180 180
Register : DDRIOB_DATA1 @ 0XF8000B4C

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DATA1 @ 0XF8000B4C 180 180
Register : DDRIOB_DIFF0 @ 0XF8000B50

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF0 @ 0XF8000B50 180 180
Register : DDRIOB_DIFF1 @ 0XF8000B54

Bitfield Bits Mask Value Shifted Value

IBUF_DISABLE_MODE 7:7 80 1 80

TERM_DISABLE_MODE 8:8 100 1 100

DDRIOB_DIFF1 @ 0XF8000B54 180 180

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

SRAM/NOR SET OPMODE

UART REGISTERS

Register : Baud_rate_divider_reg0 @ 0XE0001034

Bitfield Bits Mask Value Shifted Value

BDIV 7:0 ff 6 6

Baud_rate_divider_reg0 @ 0XE0001034 ff 6
Register : Baud_rate_gen_reg0 @ 0XE0001018

Bitfield Bits Mask Value Shifted Value

CD 15:0 ffff 3e 3e

Baud_rate_gen_reg0 @ 0XE0001018 ffff 3e
Register : Control_reg0 @ 0XE0001000

Bitfield Bits Mask Value Shifted Value

STPBRK 8:8 100 0 0

STTBRK 7:7 80 0 0

RSTTO 6:6 40 0 0

TXDIS 5:5 20 0 0

TXEN 4:4 10 1 10

RXDIS 3:3 8 0 0

RXEN 2:2 4 1 4

TXRES 1:1 2 1 2

RXRES 0:0 1 1 1

Control_reg0 @ 0XE0001000 1ff 17
Register : mode_reg0 @ 0XE0001004

Bitfield Bits Mask Value Shifted Value

CHMODE 9:8 300 0 0

NBSTOP 7:6 c0 0 0

PAR 5:3 38 4 20

CHRL 2:1 6 0 0

CLKS 0:0 1 0 0

mode_reg0 @ 0XE0001004 3ff 20

QSPI REGISTERS

Register : Config_reg @ 0XE000D000

Bitfield Bits Mask Value Shifted Value

Holdb_dr 19:19 80000 1 80000

Config_reg @ 0XE000D000 80000 80000

PL POWER ON RESET REGISTERS

Register : CTRL @ 0XF8007000

Bitfield Bits Mask Value Shifted Value

PCFG_POR_CNT_4K 29:29 20000000 0 0

CTRL @ 0XF8007000 20000000 0

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

MASK_DATA_0_LSW HIGH BANK [15:0]

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ps7_post_config_3_0

SLCR SETTINGS

Register : SLCR_UNLOCK @ 0XF8000008

Bitfield Bits Mask Value Shifted Value

UNLOCK_KEY 15:0 ffff df0d df0d

SLCR_UNLOCK @ 0XF8000008 ffff df0d

ENABLING LEVEL SHIFTER

Register : LVL_SHFTR_EN @ 0XF8000900

Bitfield Bits Mask Value Shifted Value

USER_LVL_INP_EN_0 3:3 8 1 8

USER_LVL_OUT_EN_0 2:2 4 1 4

USER_LVL_INP_EN_1 1:1 2 1 2

USER_LVL_OUT_EN_1 0:0 1 1 1

LVL_SHFTR_EN @ 0XF8000900 f f

FPGA RESETS TO 1

Bitfield	Bits	Mask	Value	Shifted Value
reserved_3	31:25	fe000000	7f	fe000000
reserved_FPGA_ACP_RST	24:24	1000000	1	1000000
reserved_FPGA_AXDS3_RST	23:23	800000	1	800000
reserved_FPGA_AXDS2_RST	22:22	400000	1	400000
reserved_FPGA_AXDS1_RST	21:21	200000	1	200000
reserved_FPGA_AXDS0_RST	20:20	100000	1	100000
reserved_2	19:18	c0000	3	c0000
reserved_FSSW1_FPGA_RST	17:17	20000	1	20000
reserved_FSSW0_FPGA_RST	16:16	10000	1	10000
reserved_1	15:14	c000	3	c000
reserved_FPGA_FMSW1_RST	13:13	2000	1	2000
reserved_FPGA_FMSW0_RST	12:12	1000	1	1000
reserved_FPGA_DMA3_RST	11:11	800	1	800
reserved_FPGA_DMA2_RST	10:10	400	1	400
reserved_FPGA_DMA1_RST	9:9	200	1	200
reserved_FPGA_DMA0_RST	8:8	100	1	100
reserved	7:4	f0	f	f0
FPGA3_OUT_RST	3:3	8	1	8
FPGA2_OUT_RST	2:2	4	1	4
FPGA1_OUT_RST	1:1	2	1	2
FPGA0_OUT_RST	0:0	1	1	1
FPGA_RST_CTRL @ 0XF8000240		ffffffff		ffffffff

FPGA RESETS TO 0

Bitfield	Bits	Mask	Value
reserved_3	31:25	fe000000	0
reserved_FPGA_ACP_RST	24:24	1000000	0
reserved_FPGA_AXDS3_RST	23:23	800000	0
reserved_FPGA_AXDS2_RST	22:22	400000	0
reserved_FPGA_AXDS1_RST	21:21	200000	0
reserved_FPGA_AXDS0_RST	20:20	100000	0
reserved_2	19:18	c0000	0
reserved_FSSW1_FPGA_RST	17:17	20000	0
reserved_FSSW0_FPGA_RST	16:16	10000	0
reserved_1	15:14	c000	0
reserved_FPGA_FMSW1_RST	13:13	2000	0
reserved_FPGA_FMSW0_RST	12:12	1000	0
reserved_FPGA_DMA3_RST	11:11	800	0
reserved_FPGA_DMA2_RST	10:10	400	0
reserved_FPGA_DMA1_RST	9:9	200	0
reserved_FPGA_DMA0_RST	8:8	100	0
reserved	7:4	f0	0
FPGA3_OUT_RST	3:3	8	0
FPGA2_OUT_RST	2:2	4	0
FPGA1_OUT_RST	1:1	2	0
FPGA0_OUT_RST	0:0	1	0
FPGA_RST_CTRL @ 0XF8000240		ffffffff

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register : SLCR_LOCK @ 0XF8000004

Bitfield Bits Mask Value Shifted Value

LOCK_KEY 15:0 ffff 767b 767b

SLCR_LOCK @ 0XF8000004 ffff 767b

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_t_rc	5:0	3f	1b	1b
reg_ddrc_t_rfc_min	13:6	3fc0	56	1580
reg_ddrc_post_selfref_gap_x32	20:14	1fc000	10	40000
DRAM_param_reg0 @ 0XF8006014		1fffff		4159b

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_final_wait_x32	6:0	7f	7	7
reg_ddrc_pre_ocd_x32	10:7	780	0	0
reg_ddrc_t_mrd	13:11	3800	4	2000
DRAM_init_param @ 0XF8006028		3fff		2007

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_emr2	15:0	ffff	8	8
reg_ddrc_emr3	31:16	ffff0000	0	0
DRAM_EMR_reg @ 0XF800602C		ffffffff		8

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_mr	15:0	ffff	930	930
reg_ddrc_emr	31:16	ffff0000	4	40000
DRAM_EMR_MR_reg @ 0XF8006030		ffffffff		40930

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dll_calib_to_min_x1024	7:0	ff	1	1
reg_ddrc_dll_calib_to_max_x1024	15:8	ff00	1	100
reg_ddrc_dis_dll_calib	16:16	10000	0	0
DLL_calib @ 0XF8006058		1ffff		101

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_rd_odt_delay	3:0	f	3	3
reg_ddrc_wr_odt_delay	7:4	f0	0	0
reg_ddrc_rd_odt_hold	11:8	f00	0	0
reg_ddrc_wr_odt_hold	15:12	f000	5	5000
ODT_delay_hold @ 0XF800605C		ffff		5003

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_go2critical_hysteresis	12:5	1fe0	0	0
reg_arb_go2critical_en	17:17	20000	1	20000
ctrl_reg2 @ 0XF8006064		21fe0		20000

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_wrlvl_ww	7:0	ff	41	41
reg_ddrc_rdlvl_rr	15:8	ff00	41	4100
reg_ddrc_dfi_t_wlmrd	25:16	3ff0000	28	280000
ctrl_reg3 @ 0XF8006068		3ffffff		284141

Bitfield	Bits	Mask	Value	Shifted Value
dfi_t_ctrlupd_interval_min_x1024	7:0	ff	10	10
dfi_t_ctrlupd_interval_max_x1024	15:8	ff00	16	1600
ctrl_reg4 @ 0XF800606C		ffff		1610

Bitfield	Bits	Mask	Value	Shifted Value
refresh_timer0_start_value_x32	11:0	fff	0	0
refresh_timer1_start_value_x32	23:12	fff000	8	8000
CHE_REFRESH_TIMER01 @ 0XF80060A0		ffffff		8000

Bitfield	Bits	Mask	Value	Shifted Value
t_zq_short_interval_x1024	19:0	fffff	cb73	cb73
dram_rstn_x1024	27:20	ff00000	69	6900000
CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8		fffffff		690cb73

Bitfield	Bits	Mask	Value	Shifted Value
deeppowerdown_en	0:0	1	0	0
deeppowerdown_to_x1024	8:1	1fe	ff	1fe
deep_pwrdwn_reg @ 0XF80060AC		1ff		1fe

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_2t_delay	8:0	1ff	0	0
reg_ddrc_skip_ocd	9:9	200	1	200
reg_ddrc_dis_pre_bypass	10:10	400	0	0
reg_2d @ 0XF80060B4		7ff		200

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_dfi_t_rddata_en	4:0	1f	6	6
reg_ddrc_dfi_t_ctrlup_min	14:5	7fe0	3	60
reg_ddrc_dfi_t_ctrlup_max	24:15	1ff8000	40	200000
dfi_timing @ 0XF80060B8		1ffffff		200066

Bitfield	Bits	Mask	Value
Clear_Uncorrectable_DRAM_ECC_error	0:0	1	0
Clear_Correctable_DRAM_ECC_error	1:1	2	0
CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4		3

Bitfield	Bits	Mask	Value
CORR_ECC_LOG_VALID	0:0	1	0
ECC_CORRECTED_BIT_NUM	7:1	fe	0
CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8		ff

Bitfield	Bits	Mask	Value	Shifted Value
UNCORR_ECC_LOG_VALID	0:0	1	0	0
CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC		1		0

Bitfield	Bits	Mask	Value
STAT_NUM_CORR_ERR	15:8	ff00	0
STAT_NUM_UNCORR_ERR	7:0	ff	0
CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0		ffff

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_ecc_mode	2:0	7	0	0
reg_ddrc_dis_scrub	3:3	8	1	8
ECC_scrub @ 0XF80060F4		f		8

Bitfield	Bits	Mask	Value
reg_phy_dif_on	3:0	f	0
reg_phy_dif_off	7:4	f0	0
phy_rcvr_enable @ 0XF8006114		ff

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wrlvl_init_ratio	9:0	3ff	3	3
reg_phy_gatelvl_init_ratio	19:10	ffc00	cf	33c00
phy_init_ratio @ 0XF800612C		fffff		33c03

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_rd_dqs_slave_ratio	9:0	3ff	35	35
reg_phy_rd_dqs_slave_force	10:10	400	0	0
reg_phy_rd_dqs_slave_delay	19:11	ff800	0	0
phy_rd_dqs_cfg @ 0XF8006140		fffff		35

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wr_dqs_slave_ratio	9:0	3ff	83	83
reg_phy_wr_dqs_slave_force	10:10	400	0	0
reg_phy_wr_dqs_slave_delay	19:11	ff800	0	0
phy_wr_dqs_cfg @ 0XF8006154		fffff		83

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_fifo_we_slave_ratio	10:0	7ff	124	124
reg_phy_fifo_we_in_force	11:11	800	0	0
reg_phy_fifo_we_in_delay	20:12	1ff000	0	0
phy_we_cfg @ 0XF8006168		1fffff		124

Bitfield	Bits	Mask	Value	Shifted Value
reg_phy_wr_data_slave_ratio	9:0	3ff	c3	c3
reg_phy_wr_data_slave_force	10:10	400	0	0
reg_phy_wr_data_slave_delay	19:11	ff800	0	0
wr_data_slv @ 0XF800617C		fffff		c3

Bitfield	Bits	Mask	Value
reg_ddrc_lpddr2	0:0	1	0
reg_ddrc_per_bank_refresh	1:1	2	0
reg_ddrc_derate_enable	2:2	4	0
reg_ddrc_mr4_margin	11:4	ff0	0
lpddr_ctrl0 @ 0XF80062A8		ff7

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_mr4_read_interval	31:0	0	0	0
lpddr_ctrl1 @ 0XF80062AC		0		0

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_min_stable_clock_x1	3:0	f	5	5
reg_ddrc_idle_after_reset_x32	11:4	ff0	12	120
reg_ddrc_t_mrw	21:12	3ff000	5	5000
lpddr_ctrl2 @ 0XF80062B0		3fffff		5125

Bitfield	Bits	Mask	Value	Shifted Value
reg_ddrc_max_auto_init_x1024	7:0	ff	a8	a8
reg_ddrc_dev_zqinit_x32	17:8	3ff00	12	1200
lpddr_ctrl3 @ 0XF80062B4		3ffff		12a8

Bitfield	Bits	Mask	Value	Shifted Value
DONE	13:13	2000	1	2000
DDRIOB_DCI_STATUS @ 0XF8000B74		2000		2000