Core Statistics |
Core Type=chipscope_icon_v1_06_a |
c_build_revision=0 |
c_constraint_type=external |
c_core_major_ver=1 |
c_core_minor_alpha_ver=97 |
c_core_minor_ver=2 |
c_core_type=1 |
c_example_design=false |
c_major_version=14 |
c_mfg_id=1 |
c_minor_version=5 |
c_num_control_ports=2 |
c_part_idcode_register=0 |
c_use_bufr=0 |
c_use_control0=1 |
c_use_control1=1 |
c_use_control10=0 |
c_use_control11=0 |
c_use_control12=0 |
c_use_control13=0 |
c_use_control14=0 |
c_use_control2=0 |
c_use_control3=0 |
c_use_control4=0 |
c_use_control5=0 |
c_use_control6=0 |
c_use_control7=0 |
c_use_control8=0 |
c_use_control9=0 |
c_use_ext_bscan=0 |
c_use_jtag_bufg=1 |
c_use_new_parser=0 |
c_use_sim=0 |
c_use_softbscan=0 |
c_use_unused_bscan=0 |
c_use_xst_tck_workaround=1 |
c_user_scan_chain=1 |
c_xco_list=Number_Control_Ports=2;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false |
c_xdevicefamily=zynq |
Core Type=chipscope_ila_v1_05_a |
c_build_revision=0 |
c_constraint_type=external |
c_core_major_ver=1 |
c_core_minor_alpha_ver=97 |
c_core_minor_ver=4 |
c_core_type=2 |
c_data_depth=4096 |
c_data_width=1 |
c_example_design=false |
c_ext_cap_pin_mode=0 |
c_ext_cap_rate_mode=0 |
c_ext_cap_use_reg=1 |
c_m0_tpid=0 |
c_m0_type=0 |
c_m10_tpid=10 |
c_m10_type=0 |
c_m11_tpid=11 |
c_m11_type=0 |
c_m12_tpid=12 |
c_m12_type=0 |
c_m13_tpid=13 |
c_m13_type=0 |
c_m14_tpid=14 |
c_m14_type=0 |
c_m15_tpid=15 |
c_m15_type=0 |
c_m1_tpid=1 |
c_m1_type=0 |
c_m2_tpid=2 |
c_m2_type=0 |
c_m3_tpid=3 |
c_m3_type=0 |
c_m4_tpid=4 |
c_m4_type=0 |
c_m5_tpid=5 |
c_m5_type=0 |
c_m6_tpid=6 |
c_m6_type=0 |
c_m7_tpid=7 |
c_m7_type=0 |
c_m8_tpid=8 |
c_m8_type=0 |
c_m9_tpid=9 |
c_m9_type=0 |
c_major_version=14 |
c_mcnt0_width=1 |
c_mcnt10_width=1 |
c_mcnt11_width=1 |
c_mcnt12_width=1 |
c_mcnt13_width=1 |
c_mcnt14_width=1 |
c_mcnt15_width=1 |
c_mcnt1_width=1 |
c_mcnt2_width=1 |
c_mcnt3_width=1 |
c_mcnt4_width=1 |
c_mcnt5_width=1 |
c_mcnt6_width=1 |
c_mcnt7_width=1 |
c_mcnt8_width=1 |
c_mcnt9_width=1 |
c_mfg_id=1 |
c_minor_version=5 |
c_num_ext_cap_pins=8 |
c_num_match_units=1 |
c_num_tseq_cnt=0 |
c_num_tseq_states=1 |
c_ram_type=1 |
c_srl16_type=2 |
c_tc_mcnt_width=1 |
c_timestamp_depth=512 |
c_timestamp_type=0 |
c_timestamp_width=32 |
c_trig0_width=4 |
c_trig10_width=1 |
c_trig11_width=1 |
c_trig12_width=1 |
c_trig13_width=1 |
c_trig14_width=1 |
c_trig15_width=1 |
c_trig1_width=1 |
c_trig2_width=1 |
c_trig3_width=1 |
c_trig4_width=1 |
c_trig5_width=1 |
c_trig6_width=1 |
c_trig7_width=1 |
c_trig8_width=1 |
c_trig9_width=1 |
c_tseq_cnt0_width=1 |
c_tseq_cnt1_width=1 |
c_tseq_type=0 |
c_use_atc_clkin=0 |
c_use_data=0 |
c_use_gap=0 |
c_use_inv_clk=0 |
c_use_mcnt0=0 |
c_use_mcnt1=0 |
c_use_mcnt10=0 |
c_use_mcnt11=0 |
c_use_mcnt12=0 |
c_use_mcnt13=0 |
c_use_mcnt14=0 |
c_use_mcnt15=0 |
c_use_mcnt2=0 |
c_use_mcnt3=0 |
c_use_mcnt4=0 |
c_use_mcnt5=0 |
c_use_mcnt6=0 |
c_use_mcnt7=0 |
c_use_mcnt8=0 |
c_use_mcnt9=0 |
c_use_rpm=1 |
c_use_storage_qual=1 |
c_use_tc_mcnt=0 |
c_use_trig0=1 |
c_use_trig1=0 |
c_use_trig10=0 |
c_use_trig11=0 |
c_use_trig12=0 |
c_use_trig13=0 |
c_use_trig14=0 |
c_use_trig15=0 |
c_use_trig2=0 |
c_use_trig3=0 |
c_use_trig4=0 |
c_use_trig5=0 |
c_use_trig6=0 |
c_use_trig7=0 |
c_use_trig8=0 |
c_use_trig9=0 |
c_use_trig_out=1 |
c_use_trigdata0=1 |
c_use_trigdata1=0 |
c_use_trigdata10=0 |
c_use_trigdata11=0 |
c_use_trigdata12=0 |
c_use_trigdata13=0 |
c_use_trigdata14=0 |
c_use_trigdata15=0 |
c_use_trigdata2=0 |
c_use_trigdata3=0 |
c_use_trigdata4=0 |
c_use_trigdata5=0 |
c_use_trigdata6=0 |
c_use_trigdata7=0 |
c_use_trigdata8=0 |
c_use_trigdata9=0 |
c_xco_list=Component_Name=chipscope_ila_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=true;Enable_Trigger_Output_Port=true;Sample_On=Rising;Sample_Data_Depth=4096;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=4;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false |
c_xdevicefamily=zynq |
Core Type=chipscope_vio_v1_05_a |
c_async_in_width=5 |
c_async_out_width=8 |
c_build_revision=0 |
c_constraint_type=external |
c_core_major_ver=1 |
c_core_minor_alpha_ver=97 |
c_core_minor_ver=2 |
c_core_type=9 |
c_example_design=false |
c_major_version=14 |
c_mfg_id=1 |
c_minor_version=5 |
c_srl16_type=2 |
c_sync_in_width=8 |
c_sync_out_width=1 |
c_use_async_in=1 |
c_use_async_out=0 |
c_use_inv_clk=0 |
c_use_sync_in=0 |
c_use_sync_out=1 |
c_xco_list=Component_Name=chipscope_vio_0;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=true;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=1;Asynchronous_Input_Port_Width=5;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false |
c_xdevicefamily=zynq |
Core Type=processing_system7 |
C_APU_PERIPHERAL_FREQMHZ=666.666667 |
C_CAN_PERIPHERAL_FREQMHZ=100 |
C_ENET0_ENET0_IO=MIO 16 .. 27 |
C_ENET0_GRP_MDIO_ENABLE=1 |
C_ENET0_GRP_MDIO_IO=MIO 52 .. 53 |
C_ENET0_PERIPHERAL_ENABLE=1 |
C_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps |
C_FPGA0_PERIPHERAL_FREQMHZ=50.000000 |
C_FPGA1_PERIPHERAL_FREQMHZ=50.000000 |
C_FPGA2_PERIPHERAL_FREQMHZ=50.000000 |
C_FPGA3_PERIPHERAL_FREQMHZ=50.000000 |
C_GPIO_GPIO_IO=MIO |
C_GPIO_PERIPHERAL_ENABLE=1 |
C_I2C0_PERIPHERAL_ENABLE=0 |
C_PJTAG_PERIPHERAL_ENABLE=0 |
C_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V |
C_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V |
C_PRESET_FPGA_PARTNUMBER=xc7z020clg484-1 |
C_PRESET_FPGA_SPEED=-1 |
C_PRESET_GLOBAL_CONFIG=Default |
C_PRESET_GLOBAL_DEFAULT=powerup |
C_QSPI_PERIPHERAL_ENABLE=1 |
C_QSPI_PERIPHERAL_FREQMHZ=200.000000 |
C_QSPI_QSPI_IO=MIO 1 .. 6 |
C_SD0_GRP_CD_ENABLE=1 |
C_SD0_GRP_CD_IO=MIO 47 |
C_SD0_GRP_POW_ENABLE=0 |
C_SD0_GRP_WP_ENABLE=1 |
C_SD0_GRP_WP_IO=MIO 46 |
C_SD0_PERIPHERAL_ENABLE=1 |
C_SDIO_PERIPHERAL_FREQMHZ=50 |
C_TTC0_PERIPHERAL_ENABLE=1 |
C_TTC0_TTC0_IO=EMIO |
C_UART1_GRP_FULL_ENABLE=0 |
C_UART1_PERIPHERAL_ENABLE=1 |
C_UART1_UART1_IO=MIO 48 .. 49 |
C_UART_PERIPHERAL_FREQMHZ=50 |
C_UIPARAM_DDR_BL=8 |
C_UIPARAM_DDR_BOARD_DELAY0=0.41 |
C_UIPARAM_DDR_BOARD_DELAY1=0.411 |
C_UIPARAM_DDR_BOARD_DELAY2=0.341 |
C_UIPARAM_DDR_BOARD_DELAY3=0.358 |
C_UIPARAM_DDR_CL=7 |
C_UIPARAM_DDR_CWL=6 |
C_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061 |
C_UIPARAM_DDR_DRAM_WIDTH=16 Bits |
C_UIPARAM_DDR_FREQ_MHZ=533.333313 |
C_UIPARAM_DDR_MEMORY_TYPE=DDR 3 |
C_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E |
C_UIPARAM_DDR_ROW_ADDR_COUNT=14 |
C_UIPARAM_DDR_SPEED_BIN=DDR3_1066F |
C_UIPARAM_DDR_TRAIN_DATA_EYE=1 |
C_UIPARAM_DDR_TRAIN_READ_GATE=1 |
C_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1 |
C_UIPARAM_DDR_T_FAW=45.0 |
C_UIPARAM_DDR_T_RAS_MIN=36.0 |
C_UIPARAM_DDR_T_RC=49.5 |
C_UIPARAM_DDR_T_RCD=7 |
C_UIPARAM_DDR_T_RP=7 |
C_UIPARAM_DDR_USE_INTERNAL_VREF=1 |
C_USB0_PERIPHERAL_ENABLE=1 |
C_USB0_USB0_IO=MIO 28 .. 39 |