Project Status (10/15/2013 - 12:28:19)
Project File: system.xmp Implementation State: Programming File Generated
Module Name: system
  • Errors:
No Errors
Product Version:EDK 14.5
  • Warnings:
590 Warnings (587 new)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileTue Oct 15 12:25:40 2013020 Warnings (20 new)15 Infos (15 new)
Simgen Log File    
BitInit Log File    
System Log FileTue Oct 15 12:28:18 2013   
 
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemTue Oct 15 12:25:54 201347671710
system_chipscope_ila_0_wrapperTue Oct 15 12:25:16 2013   0
system_axi_interconnect_1_wrapperTue Oct 15 12:25:09 2013121208 0
system_irq_gen_0_wrapperTue Oct 15 12:24:58 20138484 0
system_chipscope_icon_0_wrapperTue Oct 15 12:24:47 2013   0
system_chipscope_vio_0_wrapperTue Oct 15 12:24:39 2013   0
system_processing_system7_0_wrapperTue Oct 15 12:24:32 2013 89 0
 
Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 428 106,400 1%  
    Number used as Flip Flops 427      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 442 53,200 1%  
    Number used as logic 382 53,200 1%  
        Number using O6 output only 275      
        Number using O5 output only 59      
        Number using O5 and O6 48      
        Number used as ROM 0      
    Number used as Memory 43 17,400 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 43      
            Number using O6 output only 42      
            Number using O5 output only 0      
            Number using O5 and O6 1      
    Number used exclusively as route-thrus 17      
        Number with same-slice register load 9      
        Number with same-slice carry load 8      
        Number with other load 0      
Number of occupied Slices 242 13,300 1%  
Number of LUT Flip Flop pairs used 582      
    Number with an unused Flip Flop 174 582 29%  
    Number with an unused LUT 140 582 24%  
    Number of fully used LUT-FF pairs 268 582 46%  
    Number of unique control sets 83      
    Number of slice register sites lost
        to control set restrictions
456 106,400 1%  
Number of bonded IOBs 0 200 0%  
Number of bonded IOPAD 130 130 100%  
Number of RAMB36E1/FIFO36E1s 1 140 1%  
    Number using RAMB36E1 only 1      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 0 280 0%  
Number of BUFG/BUFGCTRLs 2 32 6%  
    Number used as BUFGs 2      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 200 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 200 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 200 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 16 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 16 0%  
Number of BSCANs 1 4 25%  
Number of BUFHCEs 0 72 0%  
Number of BUFRs 0 16 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 220 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 4 0%  
Number of IN_FIFOs 0 16 0%  
Number of MMCME2_ADVs 0 4 0%  
Number of OUT_FIFOs 0 16 0%  
Number of PHASER_REFs 0 4 0%  
Number of PHY_CONTROLs 0 4 0%  
Number of PLLE2_ADVs 0 4 0%  
Number of PS7s 1 1 100%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Number of RPM macros 9      
Average Fanout of Non-Clock Nets 2.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrentTue Oct 15 12:26:14 20130157 Warnings (154 new)6 Infos (6 new)
Map ReportCurrentTue Oct 15 12:27:08 20130148 Warnings (148 new)1426 Infos (1426 new)
Place and Route ReportCurrentTue Oct 15 12:27:37 20130143 Warnings (143 new)2 Infos (2 new)
Post-PAR Static Timing ReportCurrentTue Oct 15 12:27:49 2013004 Infos (4 new)
Bitgen ReportCurrentTue Oct 15 12:28:19 20130142 Warnings (142 new)0
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/15/2013 - 12:28:19