Core Statistics |
Core Type=axi_gpio |
C_ALL_INPUTS=0 |
C_ALL_INPUTS_2=0 |
C_DOUT_DEFAULT=00000000000000000000000000000000 |
C_DOUT_DEFAULT_2=00000000000000000000000000000000 |
C_FAMILY=zynq |
C_GPIO2_WIDTH=32 |
C_GPIO_WIDTH=1 |
C_INSTANCE=axi_gpio_0 |
C_INTERRUPT_PRESENT=0 |
C_IS_DUAL=0 |
C_S_AXI_ADDR_WIDTH=32 |
C_S_AXI_DATA_WIDTH=32 |
C_TRI_DEFAULT=11111111111111111111111111111111 |
C_TRI_DEFAULT_2=11111111111111111111111111111111 |
Core Type=axi_timer |
C_COUNT_WIDTH=32 |
C_FAMILY=zynq |
C_GEN0_ASSERT=1 |
C_GEN1_ASSERT=1 |
C_INSTANCE=axi_timer_0 |
C_ONE_TIMER_ONLY=0 |
C_TRIG0_ASSERT=1 |
C_TRIG1_ASSERT=1 |
Core Type=processing_system7 |
C_APU_PERIPHERAL_FREQMHZ=666.666667 |
C_CAN_PERIPHERAL_FREQMHZ=100 |
C_ENET0_ENET0_IO=MIO 16 .. 27 |
C_ENET0_GRP_MDIO_ENABLE=1 |
C_ENET0_GRP_MDIO_IO=MIO 52 .. 53 |
C_ENET0_PERIPHERAL_ENABLE=1 |
C_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps |
C_FPGA0_PERIPHERAL_FREQMHZ=100.000000 |
C_FPGA1_PERIPHERAL_FREQMHZ=150.000000 |
C_FPGA2_PERIPHERAL_FREQMHZ=50.000000 |
C_GPIO_EMIO_GPIO_WIDTH=1 |
C_GPIO_GPIO_IO=MIO |
C_GPIO_PERIPHERAL_ENABLE=1 |
C_I2C0_PERIPHERAL_ENABLE=0 |
C_PJTAG_PERIPHERAL_ENABLE=0 |
C_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V |
C_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V |
C_PRESET_GLOBAL_CONFIG=Default |
C_PRESET_GLOBAL_DEFAULT=powerup |
C_PSCONFIG_LVL_SHFTR_EN_C_USE_CR_FABRIC=1 |
C_QSPI_PERIPHERAL_ENABLE=1 |
C_QSPI_PERIPHERAL_FREQMHZ=200.000000 |
C_QSPI_QSPI_IO=MIO 1 .. 6 |
C_SD0_GRP_CD_ENABLE=1 |
C_SD0_GRP_CD_IO=MIO 47 |
C_SD0_GRP_POW_ENABLE=0 |
C_SD0_GRP_WP_ENABLE=1 |
C_SD0_GRP_WP_IO=MIO 46 |
C_SD0_PERIPHERAL_ENABLE=1 |
C_SDIO_PERIPHERAL_FREQMHZ=50 |
C_TTC0_PERIPHERAL_ENABLE=1 |
C_TTC0_TTC0_IO=EMIO |
C_UART1_GRP_FULL_ENABLE=0 |
C_UART1_PERIPHERAL_ENABLE=1 |
C_UART1_UART1_IO=MIO 48 .. 49 |
C_UART_PERIPHERAL_FREQMHZ=50 |
C_UIPARAM_DDR_BL=8 |
C_UIPARAM_DDR_BOARD_DELAY0=0.41 |
C_UIPARAM_DDR_BOARD_DELAY1=0.411 |
C_UIPARAM_DDR_BOARD_DELAY2=0.341 |
C_UIPARAM_DDR_BOARD_DELAY3=0.358 |
C_UIPARAM_DDR_CL=7 |
C_UIPARAM_DDR_CWL=6 |
C_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009 |
C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061 |
C_UIPARAM_DDR_DRAM_WIDTH=16 Bits |
C_UIPARAM_DDR_FREQ_MHZ=533.333313 |
C_UIPARAM_DDR_MEMORY_TYPE=DDR 3 |
C_UIPARAM_DDR_PARTNO=MT41J128M16 HA-125 |
C_UIPARAM_DDR_ROW_ADDR_COUNT=14 |
C_UIPARAM_DDR_SPEED_BIN=DDR3_1066F |
C_UIPARAM_DDR_TRAIN_DATA_EYE=1 |
C_UIPARAM_DDR_TRAIN_READ_GATE=1 |
C_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1 |
C_UIPARAM_DDR_T_FAW=40 |
C_UIPARAM_DDR_T_RAS_MIN=35 |
C_UIPARAM_DDR_T_RC=48.75 |
C_UIPARAM_DDR_T_RCD=7 |
C_UIPARAM_DDR_T_RP=7 |
C_UIPARAM_DDR_USE_INTERNAL_VREF=1 |
C_USB0_PERIPHERAL_ENABLE=1 |
C_USB0_USB0_IO=MIO 28 .. 39 |