AMD Embedded Tour 2025
12 6月 2025 - 12 6月 2025
Rome, Italy
Join Avnet Silica for the AMD Embedded Tour – Rome
Unlock new possibilities in embedded design with a one-day event dedicated to engineers and innovators. Connect directly with AMD and Avnet Silica experts, explore cutting-edge solutions from strategic partners, and gain fresh perspectives from peers in your field.
Whether you’re focused on AI at the edge, system-level optimisation, or next-gen compute architectures, this event is built to help you move faster, smarter, and with greater design freedom.
Why Attend?
You’ll tackle challenges like:.
- Simplifying compute and acceleration integration
- Maximising edge performance under power constraints
- Navigating toolchains and development workflows that fit your needs
Choose from two focused tracks and explore AMD’s embedded portfolio—x86, FPGA, adaptive SoCs, and powerful design tools—tailored for real-world workloads.
Seats are limited – secure your spot today.
Date & Time
12 June 2025
Location
Radisson Blu GHR Hotel Via Domenico Chelini, 41, 00197 Roma RM, Italy
Agenda
| 08:30-09:00 | Arrival and Registration Grab your badge, coffee, and get connected. |
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| 09:00-09:30 | Welcome and Opening Remarks Setting the stage for a day of innovation, insight, and engineering excellence. Alberto Fusaschi, AMD |
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| 09:30-10:30 | AMD Embedded Portfolio - FPGAs, adaptive SoCs and x86 CPUs Overview of the AMD Embedded portfolio including the newest FPGA, adaptive SoCs families, Embedded x86 CPUs and the AI and software solutions. Thilo Ohlemueller, AMD |
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| 10:30-11:30 | AMD : The Performant, Predictable and Proven Choice Have you chosen the lowest cost or highest performance FPGA only to struggle with timing closure, power consumption, or some other avoidable problem you didn’t anticipate? Intangibles such as development tool quality, fabric efficiency, packaging, and Hard IP can make all the difference. Attend this presentation and discover why AMD FPGAs and adaptive SoCs are the Performant, Predictable, and Proven choice. Thilo Ohlemueller, AMD |
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| Track 1 | Track 2 | |
|---|---|---|
| 11:30-12:30 | AMD Cost Optimised Portfolio Explore how the AMD cost-optimised portfolio enables scalable, efficient solutions for industrial deployments. Thilo Ohlemueller, AMD |
Introduction to Versal AIE for DSP Expand your AI Engines architecture knowledge with an in-depth overview of the development cycle and methodology with a special emphasis on DSP algorithms. We’ll also demonstrate integration of the AI Engines subsystem into the Versal platform, illustrating how this amalgamation enhances the overall system efficiency. Jerry Armao, AMD |
| 12:30-13:30 | Lunch and Networking Explore live demos, meet AMD partners, and discuss real-world use cases with peers and experts. |
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| 13:30-14:30 | Why Choose AMD Embedded x86 Options and tools for building x86 based embedded solutions and illustration of the Embedded product support flow. Fabio Caccamo, AMD |
AI Engine DSP Library Tutorial Explore the open-source DSP Library for developing Digital Signal Processing applications on the AI Engine using Vitis, Vivado, and Model Composer. Emanuele Renzi, Avnet Silica |
| 14:30-15:30 | Advantech empowers AI @ The Edge Uncover key elements for deploying AI at the Edge with AMD solutions, including how the Edge SDK accelerates development and benchmarking for AI models. Marco Pavesi, Advantech |
A Quality-Driven Journey to the Future of Embedded Development with Model-Based Design Explore how MBSE and MBD improve embedded system development by managing requirements, aligning architecture, automating code generation, and ensuring quality, with a focus on FPGA-based design. Giuseppe Ridinò, MathWorks |
| 15:30-16:00 | Coffee break | |
| 16:00-17:00 | AMD 10Gb Ethernet Solution This session explores upgrading from 1G to 10G Ethernet using AMD solutions, from Zynq Ultrascale+ MPSoC to Versal MRMAC and Gen2 10G Ethernet MAC. Emanuele Renzi, Avnet Silica |
Multi gigabit links optimisation and troubleshooting Explore the key features of Error Ratio Tester (IBERT) and how to develop a strategy to optimise link performance by interpreting results from its eye-scan capabilities. Francesco Contu, Avnet Silica |
| 17:00-17:30 | Wrap-Up, Takeaways & Raffle Key insights from the day — plus a chance to win some cool prizes in our raffle! |
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Event in collaboration with:
We’ll be joined by our partners:
Registration
Registration is now closed.