Radar Signal Processing with AMD Versal SoCs | Avnet Silica
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Radar Signal Processing with AMD Versal SoCs

Radar Signal Processing with AMD Versal SoCs

online, on-demand


AI Engines and FPGA Fusion for Efficient Compute

A congested and contested spectrum, new threats, and emerging technologies are all leading to new challenges in the realm of RF signal processing for radar and electronic.

AMD has developed a new class of heterogenous product which combines VLIW SIMD processors (named AI Engines) with traditional FPGA fabric in a single device. While these devices can provide new capabilities for existing systems, they also require new design methodologies to extract the highest performance from the device.

In this informative webinar, Jason will demonstrate a Space-Time Adaptive Processing algorithm design implemented on the AMD Versal devices, along with:

  • How phased design approach can lead to very efficient use of the device
  • How combining the AI Engines and the FPGA fabric provide increased capabilities beyond that of a single fabric type.
  • Other common signal processing blocks, such as Fourier transforms and polyphase channelisers.

 

Register Now

 

Agenda

  • 16:00 – 16:05 CET - Introduction – Paul Leys (Avnet Silica)
  • 16:05 – 16:45 CET - Radar Signal Processing with AMD Versal SoCs - Jason Timpe (AMD)
  • 16:45 – 17:00 CET - Questions and Answers Session

 

Presenters

  • Jason Timpe (Radar/EW System Architect - AMD)
  • Paul Leys (Market Segment Manager, Aerospace & Defense - Avnet Silica)

 

Registration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Radar Signal Processing with AMD Versal SoCs | Avnet Silica

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