Glossary - FPGA

Analog-to-Digital Converter

Accelerated Graphics Port - An interface specification from INTEL that enables 3D-graphics to display very fast. AGP is based on PCI, but is designed especially for the high throughput requirements of 3D-graphics.

is a distortion-producing reflection caused by the fact that all frequency components higher than half the sampling-frequency are reflected in the lower range. (To avoid, a low-pass filter is required, Anti-Aliasing)

Analog Large Scale Integration - complex analog chip design

is a procedure to avoid aliasing

Opposite of a 'fuse', where a link is grown (not blown) to make a electrically connection by passing current through

Application Specific Integrated Circuit - A custom or semicustom integrated circuit, such as a cell or gate array, created for a specific application.

Application Specific Standard Part - integrated circuit (IC) for standard application (e.g. 74xx-series standard logic products)

Advanced Technology Attachment - a disk drive interface standard for IDE (Integrated Drive Electronics)

Automatic Test Pattern Generator

typically means to write back the calculated propagation delays after the place&route-process for a post-layout simulation (standard format : SDF)

Best Conditions for a timing-logic-simulation reflects 1.) max. supply-voltage 2.) min. temperature 3.) best technology process (typ. for hold-time violation check)

Ball Grid Array - type of chip connection/packaging methodology

Build-In Self Test - additional on-chip circuitry for an self-test

is a methodology allowing complete controllability and observability of the boundary pins of a JTAG compatible device via software control. This capability enables in-circuit testing without the need of bed-of-nail in-circuit test equipment. (sometimes abbreviated with BST)

Boundary-Scan PLD Programming Generator - JTAG trademark (see also IEEE 1532)

Bi-Phase Shift Keying - is a digital frequency modulation technique used for sending data over a coaxial cable network.

Bumpered Quad Flat Pack - type of chip connection/packaging methodology

a) Buffer RAM (AT&T)

is used to assemble preliminary circuits and parts to prove the feasibility of a device, circuit or system without regard to the final configuration or packaging of the parts.

Boundary Scan Description Language - language to describe the Boundary Scan behaviour of a device

Boundary Scan Test - see also "Boundary Scan"

Computer Aided Design - computer aided design tools to develop something

Computer Aided Engineering - computer aided engineering tools to develop something

Content Addressable Memory - is a kind of storage device that includes comparison logic with each bit of storage. A data value is broadcasted to all words of storage and compared with the values therein. Words that match are flagged. (Also known as "associative memory")

Ceramic Ball Grid Array - type of chip connection/packaging methodology

Ceramic Dual In-Line Package - type of chip connection/packaging methodology

Clock Data Recovery - procedure to recover clock and data from a serial bitstream

Ceramic J-Leaded Chip Carrier - type of chip connection/packaging methodology

CLocK - a global net/signal which is the heartbeat of all digital synchronous designs/circuits.

Complementary Metal-Oxide-Semiconductor - technology with two complementary unipolar (N-MOS and P-MOS) Field-Effect-Transistors (FET)

COmpressor / DECompressor - any technology for compressing and decompressing data.

Ceramic Pin Grid Array - type of chip connection/packaging methodology

Complex Programmable Logic Device - PLD architecture type

Ceramic Quad Flat Pack - type of chip connection/packaging methodology

Cyclic Redundancy Check - procedure to prevent errors at data transmissions by adding a measure of redundancy to data

Chip Scale Ball Grid Array - type of chip connection/packaging methodology

Configurable System-on-Chip

Ceramic Small-Outline Package - type of chip connection/packaging methodology

Chip Scale Package - type of chip connection/packaging methodology

CuPL - is a description language for programmable logic (PLDs)

Digital-to-Analog Converter

Double Data Rate - property of a device, that works on both clock-edges (e.g. DDR-SDRAM)

Data Encryption Standard - transmission procedure for security applications

Digital Frequency Synthesizer

Die - name for the small silicon plate inside a chip

Dual In-Line Package - type of chip connection/packaging methodology

Delay Locked Loop - digital circuitry for frequency multiply, phase-shift, ... (similar analog PLL)

Direct Memory Access/Addressing - is a method of transferring data from one memory area to another without having to go through the central processing unit.

Digital Phase Shifter

Dynamic RAM - volatile read/write memory, content only stable for some milliseconds, refreshcycles required

Design Rule Check

Digital Signal Processor - device or module to process analog signals which have been converted to digital form (audio, video, ...).

Electronic Design Automation - Application Software tools for the development of integrated circuits and systems

Electrically Erasable PLD

Electrically Erasable PROM - electrically erasable PROM

Electronic Industry Association

Embedded Logic Analyzer

Electrically PLD

Erasable PROM - by UV-light erasable PROM, normally in a windowed package

Embedded Standard Product - a device that consist of pre-determined functions customized and supported by user-configurable logic (FPGAs) on the same piece of silicon.

Fan In - is a term, that defines the input-load of the affected input, typically '1' (see "Fan Out").

Fan Out - is a term, that defines the maximum number of digital inputs (Fan In) which can be driven by the affected output.

Fine Pitch (Fine-Line) Ball Grid Array - type of chip connection/packaging methodology

Fine Pitch Ceramic Ball Grid Array - type of chip connection/packaging methodology

Fast Cycle RAM

Windowed Frit Seal Dual In-Line Package - type of chip connection/packaging methodology

Forward Error Correction - (algorithm) a class of methods for controlling errors in a one-way communication system. FEC sends extra information along with the data, which can be used by the receiver to check and correct the data.

Flash Erasable PROM - see "FLASH"

Field Effect Transistor

Fast Fourier Transform - An algorithm for computing the "Fourier transform" of a set of discrete data values given for a finite set of data points.

First-In First-Out - type of memory management

Finite Impulse Response - methodology of a digital filter

Flash - abbreviation of "Flash EPROM", like an EEPROM but faster electrically erasable (whole chip at one time)

Flip Chip Ball Grid Array - type of chip connection/packaging methodology

is a basic digital logic circuit that can storage two states (high and low) controlled by an edge-triggered input

Fine Pitch Metall Ball Grid Array - type of chip connection/packaging methodology

Fine Pitch Plastic Ball Grid Array - type of chip connection/packaging methodology

Field Programmable Logic Array - CPLD-like devices with programmable AND/OR matrix (SIGNETICS Corporation or National Semiconductors MAPL-family)

Frequency Shift Keying - the use of frequency modulation to transmit digital data. (i.e. two different carrier frequencies are used to represent '0' and '1')

Finite State Machine - a very important circuitry to realize timing-driven tasks in realtime. The three basic FSM-types are : 1.) Medvedev 2.) Moore 3.) Mealy

Fine Pitch Thin Ball Grid Array - type of chip connection/packaging methodology

a) basic element to perform logical functions, like a digital switch that can be turned open or closed depending on the input signals (min. two)

a generic term for any interface logic or protocol that connects two component blocks. Hardware designers call anything used to connect LSI or circuit blocks "glue logic".

Gunning Transceiver Logic - is a standard for electric signals in CMOS circuits that is used to provide high data transfer speeds with small voltage swings.

Hard Array Logic - hardwired/masked PAL-device

Hardware Description Language - a kind of language used for the conceptual design of integrated circuits (i.e. VHDL and Verilog).

- is the succeeding time value, typically for a register (D-FlipFlop), to avoid metastability after a data-transfer into the register-cell (see also "setup time")

Heat-Sink Quad Flat Pack - type of chip connection/packaging methodology

Heat-Sink Small-Outline Package - type of chip connection/packaging methodology

Heat-Sink Shrink Small-Outline Package - type of chip connection/packaging methodology

High Speed Transceiver Logic - a high speed interface standard (JEDEC standard EIA/JESD8-6)

Heat-Sink Thin Shrink Small-Outline Package - type of chip connection/packaging methodology

Integrated Bus Analyzer - on-chip debugging tool

In-Circuit Reconfigurability - possibility to reconfigure a device, which is PCB-mounted

Integrated Logic Analyzer - on-chip debugging tool

Intellectual Property - a IP-core is a hardwired or soft-based (sourcecode or netlist) reusable circuitry that can be implemented in a new chip design

In System Programmable - property of a device, that is in-system programmable

The Joint Electron Device Engineering Council was originally created in 1960 as a joint activity between EIA an NEMA, to cover the standardization of discrete semiconductor devices and later expanded in 1970 to include integrated circuits. www.jedec.org

Joint Test Action Group - a standard specifying how to control and monitor the pins of compliant devices on a circuit board. Created in 1993. (IEEE standard 1149.1 and 1532 )

is a basic digital logic circuit that can storage two states (high and low) controlled by an level-triggered input (Latch-Up Effect)

Linear Feedback Shift Register - usually used for generating sequences for scrambling / descrambling methods

Low Profile Quad Flat Pack - type of chip connection/packaging methodology

Least Significant Bit

Look-Up Table - an array or matrix of fix (complex) data-values that can be read out (very fast) by addressing them through input data-values

Low Voltage CMOS

Low Voltage Differential Signalling - low-power & low-noise differential signalling technology for high speed transmission

Low Voltage Positive Emitter Coupled Logic - low-voltage PECL

Low Voltage Transistor-Transistor Logic

Military and Aerospace Applications of PLDs

Metall Ball Grid Array - type of chip connection/packaging methodology

Multi Chip Package - package with two or more dies inside

Molded Dual In-Line Package - type of chip connection/packaging methodology

Million Instructions Per Second - Indicator for computing performance

Metal Oxide Semiconductor Field Effect Transistor - is a transistor in which the conducting channel is insulated from the gate terminal by a layer of oxide. Therefore, it does not conduct even if a reverse voltage is applied to the gate.

Mask Programmable Gate Array

Microprocessor Interface

Mask-Programmed Logic Devices - masked versions of programmable logic devices

Metal Quad Flat Pack - type of chip connection/packaging methodology

Most Significant Bit

Mini Small-Outline Package - type of chip connection/packaging methodology

N-MOS - abbreviation of N-channel MOSFET (see also "CMOS" and "P-MOS")

NASA Electronic Parts & Packaging

Non-Recurring Engineering costs - e.g.: the costs to design and manufacture the process-masks for an ASIC are NRE-costs

On-Chip Memory

One Time Programmable - property of a device which is not reprogrammable or erasable

P-MOS - abbreviation of P-channel MOSFET (see also "CMOS" and "N-MOS")

- is an early hardware description language (HDL), used for PAL-devices introduced by Monolithic Memories (MMI). Developed by John Birkner in the early 1980s.

Place-And-Route

Plastic Ball Grid Array - type of chip connection/packaging methodology

Printed Circuit Board

Peripheral Component Interconnect - a personal computer loacl bus designed by Intel

Plastic Dual In-Line Package - type of chip connection/packaging methodology

Positive Emitter Coupled Logic - a high speed interface standard

Pin Grid Array - type of chip connection/packaging methodology

Programmable Interconnect Point - to program a link between two crossing nets

Programmable Logic Array - PLD device with SPLD-architecture, where the AND- and OR-matrix is programmable

Plastic J-Leaded Chip Carrier - type of chip connection/packaging methodology

Programmable Logic Device - topic term for all SPLDs, CPLDs and FPGAs.

Phase Locked Loop - analog circuitry to multiply/divide frequencies phase-locked

Programmable Logic Sequencer

Plastic Pin Grid Array - type of chip connection/packaging methodology

Plastic Quad Flat Pack - type of chip connection/packaging methodology

PRogrammable Electronics Performance Corporation - organization founded in 1992 to specify benchmarks for programmable logic devices

Programmable ROM - on-time programmable (OTP) memory

Programmable Sequence Generator

Quad Data Rate - known from QDR-SRAMs which have two independent DDR (double-data-rate) ports

Qualified Manufacturer Listing

Random Access Memory - random read/write memory

Reduced Latency DRAM - low latency high performance DRAM with SRAM-like random access (co-developed by Micron & Infineon) www.rldram.com

Read Only Memory - memory with fix content

Plastic PoweR Quad Flat Pack - type of chip connection/packaging methodology

ReSeT - a global net/signal to (re)set a synchronous digital circuitry into a defined state. There are two kinds of reset, asynchronous or synchronous.

Register Transfer Level - a kind of hardware description language used in describing the registers of a digital electronic system, and the way in which data is transferred between the registers.

Standard Delay Format - is an IEEE-standard for the representation and interpretation of timing data for use at any stage of an electronic design process, especially during timing simulations.

Shrink Dual In-Line Package - type of chip connection/packaging methodology

Synchronous DRAM - volatile memory with fast synchronous interface, content only stable for some milliseconds, refreshcycles required

Schematic Design Tool

Serializer Deserializer - fast serial receiver/transmitter hardware

- is the preceding time value, typically for a register (D-FlipFlop), to avoid metastability before a data-transfer into the register-cell (see also "hold time")

Surface Mount Technology - for PCBs

System on Chip

Small-Outline Integrated Circuit - type of chip connection/packaging methodology

Small-Outline Integrated Circuit with J-Leads - type of chip connection/packaging methodology

Small-Outline Package - type of chip connection/packaging methodology

System On Programmable Chip - name for a PLD with high densities and embedded structures on one chip

a) Simple PLD - PLD architecture-type

Shrink Quad Flat Pack - type of chip connection/packaging methodology

Static RAM - volatile memory (synchronous or asynchronous interfaces possible), content only stable at power-on

Shrink Small-Outline Integrated Circuit - type of chip connection/packaging methodology

Shrink Small-Outline Package - type of chip connection/packaging methodology

Solid State Track Link

Static Timing Analysis - the calculation of the longest or critical pathes of a design, supported by CAD/CAE-tools

Test Access Port - i.e. for JTAG BST

Typical Conditions for a timing-logic-simulation reflects 1.) typ. supply-voltage 2.) room-temperature 3.) nominal technology process

Tool Command Language - mainly used as a script file to control CAE-tools or give additional project informations, constraints or assignments

Thin Quad Flat Pack - type of chip connection/packaging methodology

Thin Small-Outline Package - type of chip connection/packaging methodology

Thin Shrink Small-Outline Package - type of chip connection/packaging methodology

Ultra Fin-Line Ball Grid Array - type of chip connection/packaging methodology

Ultra Large Scale Integration - superlative of VLSI

is a hardware description language for digital electronic design and gate-level-netlist

VHSIC Hardware Description Language - standardized language for ASIC/PLD-designers (IEEE 1076)

Very High Speed Integrated Circuit

Very Large Scale Integration - the process of placing thousands of electronic components on a single chip.

Very Thin Quad Flat Pack - type of chip connection/packaging methodology

Very Small-Outline Package - type of chip connection/packaging methodology

Verification and Simulation Tool

Worst Conditions for a timing-logic-simulation reflects 1.) min. supply-voltage 2.) max. temperature 3.) worst technology process (typ. for setup-time violation check)

Zero Bus Turnaround - is a synchronous SRAM architecture optimized for networking and telecommunications applications